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AM5728 Datasheet(PDF) 322 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 322 Page - Texas Instruments

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mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SDR251
SDR252L
SDR252H
HSSDR255
SDR256
SDR255
SDR256
vayu_mmc1_08
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SDR254
SDR258
SDR253
SDR257
SDR251
SDR252H
SDR252L
vayu_mmc1_07
322
AM5729, AM5728, AM5726
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
Table 7-96. Timing Requirements for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SDR253
tsu(cmdV-clkH)
Setup time, mmc1_cmd valid before mmc1_clk rising clock
edge
5.3
ns
SDR254
th(clkH-cmdV)
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
1.6
ns
SDR257
tsu(dV-clkH)
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock
edge
5.3
ns
SDR258
th(clkH-dV)
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock
edge
Pad
Loopbac
k Clock
1.6
ns
Internal
Loopbac
k Clock
1.6
ns
Table 7-97. Switching Characteristics for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR251
fop(clk)
Operating frequency, mmc1_clk
48
MHz
SDR252
H
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P-
0.185
(1)
ns
SDR252L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P-
0.185
(1)
ns
SDR255
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-8.8
6.6
ns
SDR256
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
(1) P = output mmc1_clk period in ns
Figure 7-66. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
Figure 7-67. MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
7.23.1.5 UHS-I SDR50, 4-bit data, half-cycle
Table 7-98 and Table 7-99 present Timing requirements and Switching characteristics for MMC1 - SDR50
in receiver and transmitter mode (see Figure 7-68 and Figure 7-69).



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