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AM5728 Datasheet(PDF) 321 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 321 Page - Texas Instruments |
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321 / 415 page  SDR122 SDR121 SDR120 SDR123 SDR124 mmc1_clk mmc1_cmd mmc1_dat[3:0] vayu_mmc1_06 SDR122 SDR121 SDR120 SDR126 SDR125 SDR128 SDR127 mmc1_clk mmc1_cmd mmc1_dat[3:0] vayu_mmc1_05 321 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-94. Timing Requirements for MMC1 - SD Card SDR12 Mode (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR127 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 25.99 ns SDR128 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge Pad Loopbac k Clock 1.6 ns Internal Loopbac k Clock 1.6 ns Table 7-95. Switching Characteristics for MMC1 - SD Card SDR12 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR120 fop(clk) Operating frequency, mmc1_clk 24 MHz SDR121 tw(clkH) Pulse duration, mmc1_clk high 0.5*P- 0.185 (1) ns SDR122 tw(clkL) Pulse duration, mmc1_clk low 0.5*P- 0.185 (1) ns SDR123 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -19.13 16.93 ns SDR124 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -19.13 16.93 ns (1) P = output mmc1_clk period in ns Figure 7-64. MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode Figure 7-65. MMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode 7.23.1.4 SDR25, 4-bit data, half-cycle Table 7-96 and Table 7-97 present Timing requirements and Switching characteristics for MMC1 - SDR25 in receiver and transmitter mode (see Figure 7-66 and Figure 7-67). |
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