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AM5728 Datasheet(PDF) 360 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 360 Page - Texas Instruments |
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360 / 415 page  360 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated 7.25.6 PRU-ICSS Manual Functional Mapping NOTE To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM. The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module Chapter in the Device TRM. Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU0 Direct Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-156 Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Output mode for a definition of the Manual modes. Table 7-156 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-156. Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Output mode BALL BALL NAME PR1_PRU0_DIR_OUT_MANUAL CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 13 AG3 vin1a_d10 0 600 CFG_VIN1A_D10_OUT pr1_pru0_gpo7 AG5 vin1a_d11 0 0 CFG_VIN1A_D11_OUT pr1_pru0_gpo8 AF2 vin1a_d12 0 2700 CFG_VIN1A_D12_OUT pr1_pru0_gpo9 AF6 vin1a_d13 0 200 CFG_VIN1A_D13_OUT pr1_pru0_gpo10 AF3 vin1a_d14 0 800 CFG_VIN1A_D14_OUT pr1_pru0_gpo11 AF4 vin1a_d15 0 0 CFG_VIN1A_D15_OUT pr1_pru0_gpo12 AF1 vin1a_d16 0 100 CFG_VIN1A_D16_OUT pr1_pru0_gpo13 AE3 vin1a_d17 0 300 CFG_VIN1A_D17_OUT pr1_pru0_gpo14 AE5 vin1a_d18 0 0 CFG_VIN1A_D18_OUT pr1_pru0_gpo15 AE1 vin1a_d19 0 400 CFG_VIN1A_D19_OUT pr1_pru0_gpo16 AE2 vin1a_d20 0 300 CFG_VIN1A_D20_OUT pr1_pru0_gpo17 AE6 vin1a_d21 0 500 CFG_VIN1A_D21_OUT pr1_pru0_gpo18 AD2 vin1a_d22 0 0 CFG_VIN1A_D22_OUT pr1_pru0_gpo19 AD3 vin1a_d23 0 500 CFG_VIN1A_D23_OUT pr1_pru0_gpo20 AH6 vin1a_d3 0 1600 CFG_VIN1A_D3_OUT pr1_pru0_gpo0 AH3 vin1a_d4 0 2800 CFG_VIN1A_D4_OUT pr1_pru0_gpo1 AH5 vin1a_d5 0 0 CFG_VIN1A_D5_OUT pr1_pru0_gpo2 AG6 vin1a_d6 0 0 CFG_VIN1A_D6_OUT pr1_pru0_gpo3 AH4 vin1a_d7 0 0 CFG_VIN1A_D7_OUT pr1_pru0_gpo4 AG4 vin1a_d8 0 0 CFG_VIN1A_D8_OUT pr1_pru0_gpo5 AG2 vin1a_d9 0 0 CFG_VIN1A_D9_OUT pr1_pru0_gpo6 Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Direct Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-157 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode for a definition of the Manual modes. Table 7-157 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. |
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