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AM5728 Datasheet(PDF) 362 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 362 Page - Texas Instruments |
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362 / 415 page  362 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-158. Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Input mode (continued) BALL BALL NAME PR1_PRU0_DIR_IN_MANUAL CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 AH6 vin1a_d3 0 600 CFG_VIN1A_D3_IN pr1_pru0_gpi0 AH3 vin1a_d4 0 0 CFG_VIN1A_D4_IN pr1_pru0_gpi1 AH5 vin1a_d5 0 900 CFG_VIN1A_D5_IN pr1_pru0_gpi2 AG6 vin1a_d6 0 400 CFG_VIN1A_D6_IN pr1_pru0_gpi3 AH4 vin1a_d7 0 500 CFG_VIN1A_D7_IN pr1_pru0_gpi4 AG4 vin1a_d8 0 0 CFG_VIN1A_D8_IN pr1_pru0_gpi5 AG2 vin1a_d9 0 0 CFG_VIN1A_D9_IN pr1_pru0_gpi6 Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-159 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode for a definition of the Manual modes. Table 7-159 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-159. Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode BALL BALL NAME PR1_PRU1_DIR_IN_MANUAL CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 D3 vin2a_d10 0 1600 CFG_VIN2A_D10_IN pr1_pru1_gpi7 F6 vin2a_d11 0 1000 CFG_VIN2A_D11_IN pr1_pru1_gpi8 D5 vin2a_d12 0 1400 CFG_VIN2A_D12_IN pr1_pru1_gpi9 C2 vin2a_d13 0 800 CFG_VIN2A_D13_IN pr1_pru1_gpi10 C3 vin2a_d14 0 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11 C4 vin2a_d15 0 1600 CFG_VIN2A_D15_IN pr1_pru1_gpi12 B2 vin2a_d16 0 1200 CFG_VIN2A_D16_IN pr1_pru1_gpi13 D6 vin2a_d17 0 1500 CFG_VIN2A_D17_IN pr1_pru1_gpi14 C5 vin2a_d18 0 1000 CFG_VIN2A_D18_IN pr1_pru1_gpi15 A3 vin2a_d19 0 1100 CFG_VIN2A_D19_IN pr1_pru1_gpi16 B3 vin2a_d20 0 700 CFG_VIN2A_D20_IN pr1_pru1_gpi17 B4 vin2a_d21 0 1300 CFG_VIN2A_D21_IN pr1_pru1_gpi18 B5 vin2a_d22 0 1400 CFG_VIN2A_D22_IN pr1_pru1_gpi19 A4 vin2a_d23 0 1300 CFG_VIN2A_D23_IN pr1_pru1_gpi20 E2 vin2a_d3 0 2100 CFG_VIN2A_D3_IN pr1_pru1_gpi0 D2 vin2a_d4 0 1000 CFG_VIN2A_D4_IN pr1_pru1_gpi1 F4 vin2a_d5 0 1700 CFG_VIN2A_D5_IN pr1_pru1_gpi2 C1 vin2a_d6 0 700 CFG_VIN2A_D6_IN pr1_pru1_gpi3 E4 vin2a_d7 0 1300 CFG_VIN2A_D7_IN pr1_pru1_gpi4 F5 vin2a_d8 0 1700 CFG_VIN2A_D8_IN pr1_pru1_gpi5 E6 vin2a_d9 0 1600 CFG_VIN2A_D9_IN pr1_pru1_gpi6 Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU0 Parallel Capture mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-160 Manual Functions Mapping for PRU-ICSS1 PRU0 Parallel Capture mode for a definition of the Manual modes. Table 7-160 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. |
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