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AM5728 Datasheet(PDF) 364 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 364 Page - Texas Instruments |
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364 / 415 page  364 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-162 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode for a definition of the Manual modes. Table 7-162 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-162. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 D7 vout1_d10 0 0 CFG_VOUT1_D10_IN pr2_pru0_gpi7 D8 vout1_d11 0 756 CFG_VOUT1_D11_IN pr2_pru0_gpi8 A5 vout1_d12 0 531 CFG_VOUT1_D12_IN pr2_pru0_gpi9 C6 vout1_d13 0 180 CFG_VOUT1_D13_IN pr2_pru0_gpi10 C8 vout1_d14 0 334 CFG_VOUT1_D14_IN pr2_pru0_gpi11 C7 vout1_d15 0 1361 CFG_VOUT1_D15_IN pr2_pru0_gpi12 B7 vout1_d16 0 488 CFG_VOUT1_D16_IN pr2_pru0_gpi13 B8 vout1_d17 0 321 CFG_VOUT1_D17_IN pr2_pru0_gpi14 A7 vout1_d18 0 254 CFG_VOUT1_D18_IN pr2_pru0_gpi15 A8 vout1_d19 0 500 CFG_VOUT1_D19_IN pr2_pru0_gpi16 C9 vout1_d20 0 716 CFG_VOUT1_D20_IN pr2_pru0_gpi17 A9 vout1_d21 0 0 CFG_VOUT1_D21_IN pr2_pru0_gpi18 B9 vout1_d22 0 404 CFG_VOUT1_D22_IN pr2_pru0_gpi19 A10 vout1_d23 0 290 CFG_VOUT1_D23_IN pr2_pru0_gpi20 G11 vout1_d3 0 226 CFG_VOUT1_D3_IN pr2_pru0_gpi0 E9 vout1_d4 0 0 CFG_VOUT1_D4_IN pr2_pru0_gpi1 F9 vout1_d5 0 365 CFG_VOUT1_D5_IN pr2_pru0_gpi2 F8 vout1_d6 0 0 CFG_VOUT1_D6_IN pr2_pru0_gpi3 E7 vout1_d7 0 218 CFG_VOUT1_D7_IN pr2_pru0_gpi4 E8 vout1_d8 0 186 CFG_VOUT1_D8_IN pr2_pru0_gpi5 D9 vout1_d9 0 308 CFG_VOUT1_D9_IN pr2_pru0_gpi6 Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-163 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode for a definition of the Manual modes. Table 7-163 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-163. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL2 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 AC5 gpio6_10 1000 3900 CFG_GPIO6_10_IN pr2_pru0_gpi0 AB4 gpio6_11 1000 4500 CFG_GPIO6_11_IN pr2_pru0_gpi1 F14 mcasp1_axr15 0 1800 CFG_MCASP1_AXR15_IN pr2_pru0_gpi20 A19 mcasp2_aclkx 0 700 CFG_MCASP2_ACLKX_IN pr2_pru0_gpi18 C15 mcasp2_axr2 0 1700 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16 A16 mcasp2_axr3 0 1800 CFG_MCASP2_AXR3_IN pr2_pru0_gpi17 A18 mcasp2_fsx 0 1100 CFG_MCASP2_FSX_IN pr2_pru0_gpi19 B19 mcasp3_axr0 0 1100 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14 |
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