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AM5728 Datasheet(PDF) 363 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 363 Page - Texas Instruments |
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363 / 415 page  363 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-160. Manual Functions Mapping for PRU-ICSS1 PRU0 Parallel Capture mode BALL BALL NAME PR1_PRU0_PAR_CAP_MANUAL CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 AG3 vin1a_d10 637 0 CFG_VIN1A_D10_IN pr1_pru0_gpi7 AG5 vin1a_d11 419 0 CFG_VIN1A_D11_IN pr1_pru0_gpi8 AF2 vin1a_d12 714 0 CFG_VIN1A_D12_IN pr1_pru0_gpi9 AF6 vin1a_d13 405 0 CFG_VIN1A_D13_IN pr1_pru0_gpi10 AF3 vin1a_d14 761 0 CFG_VIN1A_D14_IN pr1_pru0_gpi11 AF4 vin1a_d15 714 0 CFG_VIN1A_D15_IN pr1_pru0_gpi12 AF1 vin1a_d16 608 0 CFG_VIN1A_D16_IN pr1_pru0_gpi13 AE3 vin1a_d17 733 0 CFG_VIN1A_D17_IN pr1_pru0_gpi14 AE5 vin1a_d18 743 0 CFG_VIN1A_D18_IN pr1_pru0_gpi15 AE1 vin1a_d19 0 166 CFG_VIN1A_D19_IN pr1_pru0_gpi16 AH6 vin1a_d3 435 0 CFG_VIN1A_D3_IN pr1_pru0_gpi0 AH3 vin1a_d4 449 0 CFG_VIN1A_D4_IN pr1_pru0_gpi1 AH5 vin1a_d5 501 0 CFG_VIN1A_D5_IN pr1_pru0_gpi2 AG6 vin1a_d6 362 0 CFG_VIN1A_D6_IN pr1_pru0_gpi3 AH4 vin1a_d7 382 0 CFG_VIN1A_D7_IN pr1_pru0_gpi4 AG4 vin1a_d8 488 0 CFG_VIN1A_D8_IN pr1_pru0_gpi5 AG2 vin1a_d9 649 0 CFG_VIN1A_D9_IN pr1_pru0_gpi6 Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Parallel Capture mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-161 Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture mode for a definition of the Manual modes. Table 7-161 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-161. Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture mode BALL BALL NAME PR1_PRU1_PAR_CAP_MANUAL CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 D3 vin2a_d10 2693 441 CFG_VIN2A_D10_IN pr1_pru1_gpi7 F6 vin2a_d11 2580 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8 D5 vin2a_d12 2531 348 CFG_VIN2A_D12_IN pr1_pru1_gpi9 C2 vin2a_d13 2409 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10 C3 vin2a_d14 1792 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11 C4 vin2a_d15 2644 121 CFG_VIN2A_D15_IN pr1_pru1_gpi12 B2 vin2a_d16 2478 146 CFG_VIN2A_D16_IN pr1_pru1_gpi13 D6 vin2a_d17 2542 350 CFG_VIN2A_D17_IN pr1_pru1_gpi14 C5 vin2a_d18 2728 64 CFG_VIN2A_D18_IN pr1_pru1_gpi15 A3 vin2a_d19 0 0 CFG_VIN2A_D19_IN pr1_pru1_gpi16 E2 vin2a_d3 2908 562 CFG_VIN2A_D3_IN pr1_pru1_gpi0 D2 vin2a_d4 2684 0 CFG_VIN2A_D4_IN pr1_pru1_gpi1 F4 vin2a_d5 2904 234 CFG_VIN2A_D5_IN pr1_pru1_gpi2 C1 vin2a_d6 2488 0 CFG_VIN2A_D6_IN pr1_pru1_gpi3 E4 vin2a_d7 2600 124 CFG_VIN2A_D7_IN pr1_pru1_gpi4 F5 vin2a_d8 2590 547 CFG_VIN2A_D8_IN pr1_pru1_gpi5 E6 vin2a_d9 2690 248 CFG_VIN2A_D9_IN pr1_pru1_gpi6 |
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