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AM5728 Datasheet(PDF) 368 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 368 Page - Texas Instruments

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368
AM5729, AM5728, AM5726
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct
Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 7-168 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output
mode for a definition of the Manual modes.
Table 7-168 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-168. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode
BALL
BALL NAME
PR2_PRU1_DIR_OUT_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
13
U3
RMII_MHZ_50_CLK
0
2500
CFG_RMII_MHZ_50_CLK_OUT
pr2_pru1_gpo2
U4
mdio_d
0
3900
CFG_MDIO_D_OUT
pr2_pru1_gpo1
V1
mdio_mclk
0
3200
CFG_MDIO_MCLK_OUT
pr2_pru1_gpo0
U5
rgmii0_rxc
0
2600
CFG_RGMII0_RXC_OUT
pr2_pru1_gpo11
V5
rgmii0_rxctl
0
2800
CFG_RGMII0_RXCTL_OUT
pr2_pru1_gpo12
W2
rgmii0_rxd0
0
2800
CFG_RGMII0_RXD0_OUT
pr2_pru1_gpo16
Y2
rgmii0_rxd1
0
2700
CFG_RGMII0_RXD1_OUT
pr2_pru1_gpo15
V3
rgmii0_rxd2
0
2600
CFG_RGMII0_RXD2_OUT
pr2_pru1_gpo14
V4
rgmii0_rxd3
0
2700
CFG_RGMII0_RXD3_OUT
pr2_pru1_gpo13
W9
rgmii0_txc
0
3300
CFG_RGMII0_TXC_OUT
pr2_pru1_gpo5
V9
rgmii0_txctl
0
2700
CFG_RGMII0_TXCTL_OUT
pr2_pru1_gpo6
U6
rgmii0_txd0
0
2900
CFG_RGMII0_TXD0_OUT
pr2_pru1_gpo10
V6
rgmii0_txd1
0
2500
CFG_RGMII0_TXD1_OUT
pr2_pru1_gpo9
U7
rgmii0_txd2
0
3000
CFG_RGMII0_TXD2_OUT
pr2_pru1_gpo8
V7
rgmii0_txd3
0
3200
CFG_RGMII0_TXD3_OUT
pr2_pru1_gpo7
V2
uart3_rxd
0
3400
CFG_UART3_RXD_OUT
pr2_pru1_gpo3
Y1
uart3_txd
0
3000
CFG_UART3_TXD_OUT
pr2_pru1_gpo4
F11
vout1_d0
0
600
CFG_VOUT1_D0_OUT
pr2_pru1_gpo18
G10
vout1_d1
0
0
CFG_VOUT1_D1_OUT
pr2_pru1_gpo19
F10
vout1_d2
0
300
CFG_VOUT1_D2_OUT
pr2_pru1_gpo20
E11
vout1_vsync
0
1200
CFG_VOUT1_VSYNC_OUT
pr2_pru1_gpo17
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct
Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 7-169 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output
mode for a definition of the Manual modes.
Table 7-169 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-169. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode
BALL
BALL NAME
PR2_PRU1_DIR_OUT_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
13
C14
mcasp1_aclkx
0
1800
CFG_MCASP1_ACLKX_OUT
pr2_pru1_gpo7
G12
mcasp1_axr0
0
800
CFG_MCASP1_AXR0_OUT
pr2_pru1_gpo8
F12
mcasp1_axr1
0
1400
CFG_MCASP1_AXR1_OUT
pr2_pru1_gpo9
B13
mcasp1_axr10
0
2300
CFG_MCASP1_AXR10_OUT
pr2_pru1_gpo12
A12
mcasp1_axr11
0
600
CFG_MCASP1_AXR11_OUT
pr2_pru1_gpo13
E14
mcasp1_axr12
0
700
CFG_MCASP1_AXR12_OUT
pr2_pru1_gpo14
A13
mcasp1_axr13
0
1500
CFG_MCASP1_AXR13_OUT
pr2_pru1_gpo15
G14
mcasp1_axr14
0
2000
CFG_MCASP1_AXR14_OUT
pr2_pru1_gpo16



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