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AM5728 Datasheet(PDF) 372 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 372 Page - Texas Instruments |
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372 / 415 page  3 TCK TDO TDI/TMS 2 4 1 1a 1b JTAG_01 372 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated 7.27.1 IEEE 1149.1 Standard-Test-Access Port (JTAG) The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture) interface is used for BSDL testing and emulation of the device. The trstn pin only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. For maximum reliability, the device includes an internal Pulldown (IPD) on the trstn pin to ensure that trstn is always asserted upon power up and the device's internal emulation logic is always properly initialized. JTAG controllers from Texas Instruments actively drive trstn high. However, some third-party JTAG controllers may not drive trstn high but expect the use of a pullup resistor on trstn. When using this type of JTAG controller, assert trstn to initialize the device after powerup and externally drive trstn high before attempting any emulation or boundary-scan operations. The main JTAG features include: • 32KB Embedded Trace Buffer (ETB™) • 5-pin system trace interface for debug • Supports Advanced Event Triggering (AET) • All processors can be emulated via JTAG ports • All functions on EMU pins of the device: – EMU[1:0] - cross-triggering, boot mode (WIR), STM trace – EMU[4:2] - STM trace only (single direction) 7.27.1.1 JTAG Electrical Data/Timing Table 7-174, Table 7-175 and Figure 7-109 assume testing over the recommended operating conditions and electrical characteristic conditions below. Table 7-174. Timing Requirements for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 62.29 ns 1a tw(TCKH) Pulse duration, TCK high (40% of tc) 24.92 ns 1b tw(TCKL) Pulse duration, TCK low (40% of tc) 24.92 ns 3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high 6.23 ns tsu(TMS-TCK) Input setup time, TMS valid to TCK high 6.23 ns 4 th(TCK-TDI) Input hold time, TDI valid from TCK high 31.15 ns th(TCK-TMS) Input hold time, TMS valid from TCK high 31.15 ns Table 7-175. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 30.5 ns Figure 7-109. JTAG Timing |
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