AM5728 datasheet(376/415 Pages) TI1

376 / 415 page

DDR_CLK

376

AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

www.ti.com

Submit Documentation Feedback

Product Folder Links: AM5729 AM5728 AM5726

Applications, Implementation, and Layout

(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and

peak) is within the limits of the PMIC for all rails of the device.

(2) Refer to the PMIC data manual for the latest TPS659037 specifications

(3) For more information on connectivity with the TPS659037 PMIC, see the TPS659037 User’s Guide to Power AM572x (SLIU011).

(4) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power

dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj

8.2

DDR3 Board Design and Layout Guidelines

8.2.1

DDR3 General Board Layout Guidelines

To help ensure good signaling performance, consider the following board design guidelines:

•

Avoid crossing splits in the power plane.

•

Minimize Vref noise.

•

Use the widest trace that is practical between decoupling capacitors and memory module.

•

Maintain a single reference.

•

Minimize ISI by keeping impedances matched.

•

Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.

•

Use proper low-pass filtering on the Vref pins.

•

Keep the stub length as short as possible.

•

Add additional spacing for on-clock and strobe nets to eliminate crosstalk.

•

Maintain a common ground reference for all bypass and decoupling capacitors.

•

Take into account the differences in propagation delays between microstrip and stripline nets when

evaluating timing constraints.

8.2.2

DDR3 Board Design and Layout Guidelines

8.2.2.1

Board Designs

TI only supports board designs using DDR3 memory that follow the guidelines in this document. The

switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-2 and

Figure 8-1.

Table 8-2. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory

Controller

NO.

PARAMETER

MIN

MAX

UNIT

tc(DDR_CLK)

Cycle time, DDR_CLK

1.875

2.5(1)

(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and

operating frequency (see the DDR3 memory device data sheet).

Figure 8-1. DDR3 Memory Controller Clock Timing

8.2.2.2

DDR3 EMIFs

The processor contains two separate DDR3 EMIFs. This specification covers one of these EMIFs (ddr1_*)

and, thus, needs to be implemented twice, once for each EMIF. The PCB layout generally turns out to be

a semi-mirror with ddr2_* being a flipped version of ddr1_*; the only exception being the DDR3 devices

themselves are not flipped unless mounted on opposite sides of the PCB. Requirements are identical

between the two EMIFs.

AM5728 Datasheet(PDF) 376 Page - Texas Instruments

AM5728 Datasheet(HTML) 376 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL