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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

8.2.2.3

DDR3 Device Combinations

Because there are several possible combinations of device counts and single- or dual-side mounting,

Table 8-3 summarizes the supported device configurations.

Table 8-3. Supported DDR3 Device Combinations(1)

NUMBER OF DDR3 DEVICES

DDR3 DATA DEVICE WIDTH

(BITS)

MIRRORED?

DDR3 EMIF WIDTH (BITS)

Y(2)

N(4)

Y(3)

N(4)

(1) This table is per EMIF.

(2) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

(3) This is two mirrored pairs of DDR3 devices.

(4) The DDR memory connected to the DDR ECC bus does NOT need to be the same part number as the DDR memories connected to the

DDR data bus. However, some constraints do apply. When selecting a memory for the DDR ECC bus, the following restrictions must be

adhered to as compared to the DDR memories on the data bus:

–

Match the same DDR3 speed grade

–

Have an equal number of internal banks

–

Have an equal number of columns

–

Have a greater or equal number of rows

8.2.2.4

DDR3 Interface Schematic

8.2.2.4.1 32-Bit DDR3 Interface

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width

of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR

devices look like two 8-bit devices. Figure 8-2 and Figure 8-3 show the schematic connections for 32-bit

interfaces using x16 devices.

8.2.2.4.2 16-Bit DDR3 Interface

Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-2

and Figure 8-3); only the high-word DDR memories are removed and the unused DQS inputs are tied off.

When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off

the ddrx_dqsi pins to ground via a 1k-

Ω resistor and to tie off the ddrx_dqsni pins to the corresponding

vdds_ddrx supply via a 1k-

Ω resistor. This needs to be done for each byte not used. Although these

signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection

against external electrical noise causing activity on the signals.

The vdds_ddrx and ddrx_vref0 power supply pins need to be connected to their respective power supplies

even if ddrx is not being used. All other DDR interface pins can be left unconnected. Note that the

supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.

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