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AM5728 Datasheet(PDF) 371 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 371 Page - Texas Instruments |
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371 / 415 page  371 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-172. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture mode (continued) BALL BALL NAME PR2_PRU1_PAR_CAP_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 V6 rgmii0_txd1 1749 0 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9 U7 rgmii0_txd2 1410 0 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8 V7 rgmii0_txd3 1479 0 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7 V2 uart3_rxd 1124 0 CFG_UART3_RXD_IN pr2_pru1_gpi3 Y1 uart3_txd 765 0 CFG_UART3_TXD_IN pr2_pru1_gpi4 Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Parallel Capture mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-173 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture mode for a definition of the Manual modes. Table 7-173 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-173. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture mode BALL BALL NAME PR2_PRU1_PAR_CAP_MANUAL2 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 C14 mcasp1_aclkx 1959 0 CFG_MCASP1_ACLKX_IN pr2_pru1_gpi7 G12 mcasp1_axr0 3142 0 CFG_MCASP1_AXR0_IN pr2_pru1_gpi8 F12 mcasp1_axr1 2361 0 CFG_MCASP1_AXR1_IN pr2_pru1_gpi9 B13 mcasp1_axr10 2488 0 CFG_MCASP1_AXR10_IN pr2_pru1_gpi12 A12 mcasp1_axr11 2652 0 CFG_MCASP1_AXR11_IN pr2_pru1_gpi13 E14 mcasp1_axr12 2036 0 CFG_MCASP1_AXR12_IN pr2_pru1_gpi14 A13 mcasp1_axr13 2301 0 CFG_MCASP1_AXR13_IN pr2_pru1_gpi15 G14 mcasp1_axr14 0 0 CFG_MCASP1_AXR14_IN pr2_pru1_gpi16 B12 mcasp1_axr8 2581 0 CFG_MCASP1_AXR8_IN pr2_pru1_gpi10 A11 mcasp1_axr9 2565 0 CFG_MCASP1_AXR9_IN pr2_pru1_gpi11 D17 mcasp4_axr1 2580 0 CFG_MCASP4_AXR1_IN pr2_pru1_gpi0 AA3 mcasp5_aclkx 3533 2482 CFG_MCASP5_ACLKX_IN pr2_pru1_gpi1 AB3 mcasp5_axr0 3568 2725 CFG_MCASP5_AXR0_IN pr2_pru1_gpi3 AA4 mcasp5_axr1 3679 2464 CFG_MCASP5_AXR1_IN pr2_pru1_gpi4 AB9 mcasp5_fsx 3604 2091 CFG_MCASP5_FSX_IN pr2_pru1_gpi2 D18 xref_clk0 851 0 CFG_XREF_CLK0_IN pr2_pru1_gpi5 E17 xref_clk1 1966 0 CFG_XREF_CLK1_IN pr2_pru1_gpi6 7.26 System and Miscellaneous interfaces The Device includes the following System and Miscellaneous interfaces: • Sysboot Interface • System DMA Interface • Interrupt Controllers (INTC) Interface • Observability Signal (OBS) Interface 7.27 Test Interfaces The Device includes the following Test interfaces: • IEEE 1149.1 Standard-Test-Access Port (JTAG) • Trace Port Interface Unit (TPIU) • Advanced Event Triggering Interface (AET) |
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