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AM5728 Datasheet(PDF) 369 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 369 Page - Texas Instruments |
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369 / 415 page  369 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-169. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode (continued) BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 13 E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_OUT pr2_pru1_gpo17 F11 vout1_d0 0 0 CFG_VOUT1_D0_OUT pr2_pru1_gpo18 G10 vout1_d1 0 0 CFG_VOUT1_D1_OUT pr2_pru1_gpo19 F10 vout1_d2 0 0 CFG_VOUT1_D2_OUT pr2_pru1_gpo20 B12 mcasp1_axr8 0 2000 CFG_MCASP1_AXR8_OUT pr2_pru1_gpo10 A11 mcasp1_axr9 0 800 CFG_MCASP1_AXR9_OUT pr2_pru1_gpo11 D17 mcasp4_axr1 0 0 CFG_MCASP4_AXR1_OUT pr2_pru1_gpo0 AA3 mcasp5_aclkx 1000 4200 CFG_MCASP5_ACLKX_OUT pr2_pru1_gpo1 AB3 mcasp5_axr0 1000 3100 CFG_MCASP5_AXR0_OUT pr2_pru1_gpo3 AA4 mcasp5_axr1 1000 2700 CFG_MCASP5_AXR1_OUT pr2_pru1_gpo4 AB9 mcasp5_fsx 1000 2800 CFG_MCASP5_FSX_OUT pr2_pru1_gpo2 D18 xref_clk0 0 1600 CFG_XREF_CLK0_OUT pr2_pru1_gpo5 E17 xref_clk1 0 1500 CFG_XREF_CLK1_OUT pr2_pru1_gpo6 Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET1 Parallel Capture mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-170 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Parallel Capture mode for a definition of the Manual modes. Table 7-170 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-170. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Parallel Capture mode BALL BALL NAME PR2_PRU0_PAR_CAP_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 12 D7 vout1_d10 1554 0 CFG_VOUT1_D10_IN pr2_pru0_gpi7 D8 vout1_d11 1711 0 CFG_VOUT1_D11_IN pr2_pru0_gpi8 A5 vout1_d12 1562 0 CFG_VOUT1_D12_IN pr2_pru0_gpi9 C6 vout1_d13 1350 0 CFG_VOUT1_D13_IN pr2_pru0_gpi10 C8 vout1_d14 1552 0 CFG_VOUT1_D14_IN pr2_pru0_gpi11 C7 vout1_d15 1882 0 CFG_VOUT1_D15_IN pr2_pru0_gpi12 B7 vout1_d16 1525 0 CFG_VOUT1_D16_IN pr2_pru0_gpi13 B8 vout1_d17 1431 0 CFG_VOUT1_D17_IN pr2_pru0_gpi14 A7 vout1_d18 1240 0 CFG_VOUT1_D18_IN pr2_pru0_gpi15 A8 vout1_d19 0 0 CFG_VOUT1_D19_IN pr2_pru0_gpi16 G11 vout1_d3 1231 0 CFG_VOUT1_D3_IN pr2_pru0_gpi0 E9 vout1_d4 1355 0 CFG_VOUT1_D4_IN pr2_pru0_gpi1 F9 vout1_d5 1261 0 CFG_VOUT1_D5_IN pr2_pru0_gpi2 F8 vout1_d6 1016 0 CFG_VOUT1_D6_IN pr2_pru0_gpi3 E7 vout1_d7 1297 0 CFG_VOUT1_D7_IN pr2_pru0_gpi4 E8 vout1_d8 1390 0 CFG_VOUT1_D8_IN pr2_pru0_gpi5 D9 vout1_d9 1685 0 CFG_VOUT1_D9_IN pr2_pru0_gpi6 |
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