AM5728 datasheet(397/415 Pages) TI1

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AM5729, AM5728, AM5726

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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

Table 8-12. CK and ADDR_CTRL Routing Specification(2)(3)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

CARS31

A1+A2 length

500(1)

CARS32

A1+A2 skew

CARS33

A3 length

125

CARS34

A3 skew(4)

CARS35

A3 skew(5)

CARS36

A4 length

125

CARS37

A4 skew

CARS38

AS length

5(1)

CARS39

AS skew

1.3(1)

CARS310

AS+/AS- length

CARS311

AS+/AS- skew

CARS312

AT length(6)

CARS313

AT skew(7)

CARS314

AT skew(8)

CARS315

CK/ADDR_CTRL trace length

1020

CARS316

Vias per trace

3(1)

vias

CARS317

Via count difference

1(15)

vias

CARS318

Center-to-center CK to other DDR3 trace spacing(9)

CARS319

Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)

CARS320

Center-to-center ADDR_CTRL to other ADDR_CTRL trace

spacing(9)

CARS321

CK center-to-center spacing (11)(12)

CARS322

CK spacing to other net(9)

CARS323

Rcp(13)

Zo-1

Zo+1

CARS324

Rtt(13)(14)

Zo-5

Zo+5

(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of

rise time and fall time confirms desired operation.

(2) The use of vias should be minimized.

(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump

between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.

(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).

(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).

(6) While this length can be increased for convenience, its length should be minimized.

(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.

(8) CK net class only.

(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.

(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.

(11) CK spacing set to ensure proper differential impedance.

(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,

center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended

impedance, Zo.

(13) Source termination (series resistor at driver) is specifically not allowed.

(14) Termination values should be uniform across the net class.

(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal

propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.

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