AM5728 datasheet(399/415 Pages) TI1

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AM5729, AM5728, AM5726

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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

Table 8-13. Data Routing Specification(2) (continued)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

DRS312

DQSn center-to-center spacing (8) (9)

DRS313

DQSn center-to-center spacing to other net

w(5)

(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of

rise time and fall time confirms desired operation.

(2) External termination disallowed. Data termination should use built-in ODT functionality.

(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.

(4) Each DQS pair is length matched to its associated byte.

(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.

(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.

(7) This applies to spacing within the net classes of a byte.

(8) DQS pair spacing is set to ensure proper differential impedance.

(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,

center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended

impedance, Zo.

(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal

propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.

8.3

High Speed Differential Signal Routing Guidance

The

High-Speed

Interface

Layout

Guidelines

Application

Report

(SPRAAR7)

available

from

http://www.ti.com/lit/pdf/spraar7 provides guidance for successful routing of the high speed differential

signals. This includes PCB stackup and materials guidance as well as routing skew, length and spacing

limits. TI supports only designs that follow the board design guidelines contained in the application report.

8.4

Power Distribution Network Implementation Guidance

The Sitara Processor Power Distribution Networks: Implementation and Analysis (SPRAC76) available

from http://www.ti.com/lit/pdf/sprac76 provides guidance for successful implementation of the power

distribution network. This includes PCB stackup guidance as well as guidance for optimizing the selection

and placement of the decoupling capacitors. TI supports only designs that follow the board design

guidelines contained in the application report.

8.5

Thermal Solution Guidance

The Thermal Design Guide for DSP and Arm Application Processors Application Report (SPRABI3)

available from http://www.ti.com/lit/pdf/sprabi3 and the AM572x Thermal Considerations Application

Report (SPRAC53) available from http://www.ti.com/lit/pdf/sprac53 provide guidance for successful

implementation of a thermal solution for system designs that contain an AM57xx application processor.

They provide background information on common terms and methods related to thermal solutions. Test

data and thermal calculations are also provided for a sample design. TI supports only designs that follow

the system design guidelines contained in the application reports. Devices must be operated within their

rated temperature ranges at all times to maintain proper function and rated Power On Hours.

8.6

Single-Ended Interfaces

8.6.1

General Routing Guidelines

The following paragraphs detail the routing guidelines that must be observed when routing the various

functional LVCMOS interfaces.

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