AM5728 datasheet(398/415 Pages) TI1

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DQLMX3

DQLMY0

DQLMY3

DQLMY2

DB3

DQLMX2

DB2

DQ[24:31]/DM3/DQS3

DQ[16:23]/DM2/DQS2

DQLMX1

DB1

DB0

DQLMX0

DQ[8:15]/DM1/DQS1

DQ[0:7]/DM0/DQS0

DQLMY1

DB0 - DB3 represent data bytes 0 - 3.

398

AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

8.2.2.17.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew

must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces

up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,

a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as

DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four

DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length

matching is only required within each byte.

Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 8-28 shows this distance for

four loads. It is from this distance that the specifications on the lengths of the transmission lines for the

data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-13.

There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the

byte; therefore:

DQLM0 = DQLMX0 + DQLMY0

DQLM1 = DQLMX1 + DQLMY1

DQLM2 = DQLMX2 + DQLMY2

DQLM3 = DQLMX3 + DQLMY3

Figure 8-28. DQLM for Any Number of Allowed DDR3 Devices

Table 8-13. Data Routing Specification(2)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

DRS31

DB0 length

340

DRS32

DB1 length

340

DRS33

DB2 length

340

DRS34

DB3 length

340

DRS35

DBn skew(3)

DRS36

DQSn+ to DQSn- skew

DRS37

DQSn to DBn skew(3)(4)

5(10)

DRS38

Vias per trace

2(1)

vias

DRS39

Via count difference

0(10)

vias

DRS310

Center-to-center DBn to other DDR3 trace spacing(6)

w(5)

DRS311

Center-to-center DBn to other DBn trace spacing(7)

w(5)

AM5728 Datasheet(PDF) 398 Page - Texas Instruments

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