AM5728 datasheet(401/415 Pages) TI1

401 / 415 page

qspi1_sclk

qspi1_rtclk

QSPI device

clock input

QSPI device

IOx, CS#

qspi1_d[x], qspi1_cs[y]

10 Ω

Locate both R2 resistors

close together near the QSPI device

SPRS906_PCB_QSPI_01

401

AM5729, AM5728, AM5726

www.ti.com

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: AM5729 AM5728 AM5726

Applications, Implementation, and Layout

Figure 8-30. QSPI Interface High Level Schematic

(1) 0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-tuning if needed.

8.7

LJCB_REFN/P Connections

A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two

modes of Common Refclk Rx Architecture are supported:

•

External REFCLK Mode: An common external 100MHz clock source is distributed to both the Device

and the link partner

•

Output REFCLK Mode: A 100MHz HCSL clock source is output by the device and used by the link

partner

In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to

the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs.

Alternatively, an LVDS clock source can be used with the following additional requirements:

•

External AC coupling capacitors described in Table 8-14 should be populated at the ljcb_clkn /

ljcb_clkp inputs.

•

All termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer

should be followed.

In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on

the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External near-

side termination to ground described in Table 8-15 is required on both of the ljcb_clkn / ljcb_clkp outputs

in this mode.

Table 8-14. LJCB_REFN/P Requirements in External LVDS REFCLK Mode

PARAMETER

MIN

TYP

MAX

UNIT

ljcb_clkn / ljcb_clkp AC coupling capacitor value

100

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