AM5728 datasheet(402/415 Pages) TI1

402 / 415 page

Via to GND

Local ground plane

SWPS040-196

402

AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

Table 8-14. LJCB_REFN/P Requirements in External LVDS REFCLK Mode (continued)

PARAMETER

MIN

TYP

MAX

UNIT

ljcb_clkn / ljcb_clkp AC coupling capacitor package size

0402

0603

EIA(1)(2)

(1) EIA LxW units, that is, a 0402 is a 40x20 mils surface mount capacitor.

(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.

Table 8-15. LJCB_REFN/P Requirements in Output REFCLK Mode

PARAMETER

MIN

TYP

MAX

UNIT

ljcb_clkn / ljcb_clkp near-side termination to ground value

47.5

52.5

Ohms

8.8

Clock Routing Guidelines

8.8.1

32-kHz Oscillator Routing

When designing the printed-circuit board:

•

Keep the crystal as close as possible to the crystal pins X1 and X2.

•

Keep the trace lengths short and small to reduce capacitor loading and prevent unwanted noise

pickup.

•

Place a guard ring around the crystal and tie the ring to ground to help isolate the crystal from

unwanted noise pickup.

•

Keep all signals out from beneath the crystal and the X1 and X2 pins to prevent noise coupling.

•

Finally, an additional local ground plane on an adjacent PCB layer can be added under the crystal to

shield it from unwanted pickup from traces on other layers of the board. This plane must be isolated

from the regular PCB ground plane and tied to the GND pin of the RTC. The plane must not be any

larger than the perimeter of the guard ring. Make sure that this ground plane does not contribute to

significant capacitance (a few pF) between the signal line and ground on the connections that run from

X1 and X2 to the crystal.

Figure 8-31. Slow Clock PCB Requirements

8.8.2

Oscillator Ground Connection

Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in

the ground plane causes a voltage drop in the ground. Figure 8-32 shows the grounding scheme for slow

(low frequency) clock generated from the internal oscillator.

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