MAX5876/MAX5877/MAX5878 Evaluation Kits

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5

Outputs

The dual-output channels of the MAX5876/MAX5877/

MAX5878 are configured for differential current mode to

achieve the best dynamic performance. The resistor

and transformer networks at the DAC outputs are

designed to convert the differential current signals into

single-ended voltage signals with a 50

Ω output imped-

ance. When an LVDS logic-high input signal is applied

to the SELIQP/SELIQN pins, the data on the input bus

(J1 and J2) is loaded into I-DAC and the reconstructed

single-ended signal is available at the OUTPUTI SMA

connector. When an LVDS logic-low input signal is

applied to the SELIQP/SELIQN pins, the data on the

input bus is loaded into Q-DAC and the reconstructed

single-ended signal is available at the OUTPUTQ SMA

connector. When outputs OUTPUTQ and OUTPUTI are

terminated with 50

Ω external loads, the full-scale output

signal level is equal to -2dBm.

To evaluate the converter’s single-ended outputs,

remove transformers T1, T2, and install SMA connec-

tors at the OUTIP, OUTIN, OUTQP, and OUTQN loca-

tions. Probe the single-ended signals at the OUTIP and

OUTIN SMA connectors for I-DAC. Probe the single-

ended signals at the OUTQP and OUTQN SMA con-

nectors for Q-DAC. In a single-ended configuration the

of the outputs.

Power-Down Mode

The MAX5876/MAX5877/MAX5878 EV kits power-

down/normal operation mode can be configured with

jumper JU1. See Table 3 for jumper JU1 configuration.

PCB Layout

The MAX5876/MAX5877/MAX5878 EV kits are 4-layer

PCB designs optimized for high-speed signals. All

high-speed digital signal lines are routed through 100

Ω

differential impedance-matched transmission lines. All

analog output traces are routed through 50

Ω imped-

ance-matched transmission lines. The length of these

100

Ω and 50Ω transmission lines is matched to within

40 mils (1mm) to minimize layout-dependent data skew.

The PCB layout separates the digital, analog, and clock

sections of the circuit for optimum performance.

Table 2. Reference Voltage

JUMPER JU3

SHUNT POSITION

JUMPER JU4

SHUNT POSITION

REFIO PIN CONNECTION

EV KIT FUNCTION

Not installed

Not installed

Open (REFIO becomes the output of

the internal bandgap reference)

Internal 1.2V reference enabled or

connect an external reference to TP1

Installed

Installed

Connected to U2 (MAX6161)

U2 provides a precise 1.25V voltage

reference

SHUNT POSITION

PD PIN CONNECTION

EV KIT FUNCTION

1-2

Connected to DVDD2

Power-down mode

2-3

Connected to DGND

Not installed

MAX5876/MAX5877/MAX5878 have an

internal pulldown resistor

Normal operation

Table 1. Jumper JU2 TORB Configuration

SHUNT POSITION

TORB PIN CONNECTION

EV KIT FUNCTION

1-2

Connected to DVDD2

Two’s-complement digital signal input format

2-3

Connected to DGND

Not installed

MAX5876/MAX5877/MAX5878 have an

internal pulldown resistor

Offset-binary digital signal input format

Table 3. JUMPER JU1 Power-Down Configuration