GD25Q16CSFG datasheet(18/68 Pages) GIGADEVICE

18 / 68 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q16C

7.5. Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the

system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or

affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command

must be issued prior to a Write Status Register command and any other commands can't be inserted between them.

Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command

will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status

Figure 6. Write Enable for Volatile Status Register Sequence Diagram

7.6. Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-Byte address (A23-A0), and each bit is latched-in on the

rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max

frequency fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically

incremented to the next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read

with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or

Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 7. Read Data Bytes Sequence Diagram

Command

03H

CS#

SCLK

High-Z

9 10

28 29 30 31 32

MSB

34 35 36 37

23 22 21

38 39

24-bit address

MSB

Data Out1

Data Out2

CS#

SCLK

Command(50H)

High-Z

GD25Q16CSFG Datasheet(PDF) 18 Page - GigaDevice Semiconductor (Beijing) Inc.