GD25Q16CSFG datasheet(34/68 Pages) GIGADEVICE

34 / 68 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q16C

Figure 31. Program/Erase Suspend Sequence Diagram

7.27. Program/Erase Resume (PER) (7AH)

The Program/Erase Resume command must be written to resume the program or sector/block erase operation after

a Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the

SUS bit equal to 1 and the WIP bit equal to 0. After issued the SUS bit in the status register will be cleared from 1 to 0

immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or

the page will complete the program operation. The Program/Erase Resume command will be ignored unless a

Program/Erase Suspend is active. The command sequence is show in Figure32.

Figure 32. Program/Erase Resume Sequence Diagram

7.28. Erase Security Registers (44H)

The GD25Q16C provides four 256-Byte Security Registers which can be read and programmed individually. These

registers may be used by the system manufacturers to store security and other important information separately from the

main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command 

3-Byte address on SI CS# goes high. The command sequence is shown in Figure33. CS# must be driven high after the

eighth bit of the command code has been latched in, otherwise the Erase Security Registers command is not executed. As

soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase

Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed.

At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers

Command

75H

CS#

SCLK

High-Z

tSUS

Accept read command

Command

7AH

CS#

SCLK

Resume Erase/Program

GD25Q16CSFG Datasheet(PDF) 34 Page - GigaDevice Semiconductor (Beijing) Inc.