GD25VQ16CSFG datasheet(32/59 Pages) GIGADEVICE

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Uniform Sector

Dual and Quad Serial Flash

GD25VQ16C

7.24.

Continuous Read Mode Reset (CRMR) (FFH)

The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce

command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the

BBH/EBH/E7H command code.

Because the GD25VQ16C

has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the

GD25VQ16C will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the

Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence

is show in Figure29.

Figure 29. Continuous Read Mode Reset Sequence Diagram

7.25.

Read Unique ID (4BH)

The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The

Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.

The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command  3-Byte Address

(000000H) Dummy Byte128bit Unique ID Out CS# goes high.

Figure 30. Read Unique ID Sequence Diagram

Command

4BH

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

(000000H)

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Byte

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

FFH

Mode Bit Reset for Quad/Dual I/O

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