GD25VQ16CSFG datasheet(34/59 Pages) GIGADEVICE

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Uniform Sector

Dual and Quad Serial Flash

GD25VQ16C

7.28. Erase Security Registers (44H)

The GD25VQ16C provides four 256-byte Security Registers which can be erased and programmed individually.

These registers may be used by the system manufacturers to store security and other important information separately from

the main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command 

CS# goes high. The command sequence is shown in Figure33. CS# must be driven high after the eighth bit of the command

code has been latched in, otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high,

the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is

in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status

permanently locked; the Erase Security Registers command will be ignored.

Address

A23-A16

A15-A10

A9-A0

Security Registers

00000000

000000

Don’t Care

Figure 33. Erase Security Registers command Sequence Diagram

Command

44H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

GD25VQ16CSFG Datasheet(PDF) 34 Page - GigaDevice Semiconductor (Beijing) Inc.