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SVPL3R306SG - 1.0

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Page 9

SVPL3R306SG Series

6.2.4 Adjusting the Output Voltage (TRIM)

The output voltage of the converter is set with an external trim resistor connected from the TRIM pin to the AGND pin. Use the

equations or table below to choose the trim resistor value. Trim resistor tolerance of 0.1% is recommended to achieve an accurate

output voltage. The default output voltage with the TRIM pin left open is 0.8 V. The designer can adjust the output voltage from 0.8 V to

85% of the input voltage.

6.2.5 Output Capacitors

While the SVPL3R306SG is stable without external output capacitance, a minimum of 220 µF is required to meet the Performance

Specifications from section 3.2. Output capacitors for point-of-load (POL) DC/DC converters should be chosen to meet output voltage

ripple and transient requirements. Meeting the transient response requirement is accomplished by making the output impedance of the

converter sufficiently small. Given the high control bandwidth of POL converters like the SVPL series, the peak output impedance is

typically dominated by the equivalent series resistance (ESR) of the bulk output capacitance. Therefore, the output capacitors should

be chosen to set a certain maximum to

tal ESR. The total ESR is the parallel combination of the internal bulk capacitor’s ESR and that

of the added capacitors. Given the output voltage transient requirement, maximum load step, and the ESR of each bulk capacitor that

will be added, the number of added capacitors needed is calculated with the following equations:

���� =

Make sure that the added capacitance does not violate the maximum allowed output capacitance using the following equation:

3300µ����

capacitors being used are 330 µF and have a maximum ESR of 50m

Ω each.

SVPL3R306SG

+Vout (V)

Rtrim (Ω)

0.8

Open

0.9

5.80k

1.0

2.80k

1.2

1.30k

1.5

657

1.8

400

2.0

300

2.5

153

2.8

100

3.0

72.7

3.3

40.0

3.6

14.3

3.8

0.0

Parameter

Definition

ΔV

OUT

ΔI

OUT

Max load current step

Total combined parallel ESR, including internal

and added capacitors

Combined parallel ESR of the added capacitors

ESR of the internal bulk capacitor

(

43.7mΩ max under worst-case conditions)

ESR of each of the added capacitors

N

Number of added capacitors

600

− 200

600

+ 0.8