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ES222 Datasheet(PDF) 10 Page - Cyrustek corporation |
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ES222 Datasheet(HTML) 10 Page - Cyrustek corporation |
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10 / 32 page  ver. 1.2 16/07/12 10 ES222(9999counts dual) DMM Analog front end/Inrush 1.2 Read/Write command description The write command includes one ID byte with four command bytes. If the valid write ID code is received by ES222 at any time, the write command operation will be enabled. The next table shows the content of write command: (ADC1/ADC2 controlled individually) Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ID 1 1 0 0 1 0 BUZ R/W=0 W1 F3 F2 F1 F0 C1_AD1 C0_AD1 C1_AD2 C0_AD2 W2 AC_1 AC_2 Q2 Q1 Q0 B2 B1 B0 W3 VAHZ_1 VAHZ_2 FQ2_1 FQ1_1 FQ0_1 FQ2_2 FQ1_2 FQ0_2 W4 PCAL_1 PCAL_2 PEAK_1 PEAK_2 AD12IN AD21IN AD1UPIN AD2UPIN W5 SUDP2_1 SUDP1_1 SUDP0_1 SUDP2_2 SUDP1_2 SUDP0_2 AD1OFF AD2OFF W6 LPF1_1 LPF0_1 LPF1_2 LPF0_2 0 UDPD10_1 0 UDPD10_2 W7 PHSEQ_1 PHSEQ_2 IOP1 IOP0 INA FCOND SHBP 0 W8 0 0 0 C_Clamp R_FIN1M DIOVSS 0 0 Buzzer driver ON/OFF control bit: BUZ Measurement function control bit: F3/F2/F1/F0 ADC conversion rate selection: C1_AD1/C0_AD1/C1_AD2/C0_AD2 AC mode control enable bit: AC_1/AC_2 Range control bit for V/A/R/C modes: Q2/Q1/Q0 Buzzer frequency selection: B2/B1/B0 Frequency measurement for AC mode enabled control: VAHZ_1/VAHZ_2 Range control bit for FREQ mode: FQ2_1/FQ1_1/FQ0_1/ FQ2_2/FQ1_2/FQ0_2 Peak voltage detection offset calibration control bit: PCAL_1/PCAL_2 Peak hold measurement mode control bit: PEAK_1/PEAK_2 ADC1/ADC2 input channel MUX control: AD12IN/AD21IN/AD1UPIN/AD2UPIN User-defined ADC1 input channel selection: SUDP2_1/SUDP1_1/SUDP0_1 User-defined ADC2 input channel selection: SUDP2_2/SUDP1_2/SUDP0_2 ADC disabled control: AD1OFF/AD2OFF 3dB BW for low-pass-filter selection: LPF1_1/LPF0_1/LPF1_2/LPF0_2 Full scale divided by ten for UDP mode control bit: UDPD10_1/UDPD10_2 3-phase voltage measurement at 1000V range of ADC1 or ADC2: PHSEQ_1/PHSEQ_2 OP configuration control bit: IOP1/IOP0 INRUSH measurement control: INA Conductance mode enabled control at 10M Ω range: FCOND Auxiliary low-resistance detection control bit for Continuity and Diode modes: SHBP OVH1 path omitted control bit in Capacitance mode: C_Clamp Frequency mode input terminal impedance: R_FIN1M Diode measurement mode open source voltage selection: DIOVSS |
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