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AD4112BCPZ Datasheet(PDF) 5 Page - Analog Devices |
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AD4112BCPZ Datasheet(HTML) 5 Page - Analog Devices |
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5 / 58 page  Data Sheet AD4112 Rev. A | Page 5 of 58 SPECIFICATIONS AVDD = 3.0 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, VBIAS− = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock (MCLK) = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit VOLTAGE INPUTS Differential Input Voltage Range1 Specified performance −10 +10 V Functional −VREF × 10 +VREF × 10 V Absolute (Pin) Input Voltage AVDD ≥ 4.75 V −20 +20 V AVDD = 3.0 V −12 +12 V Input Impedance 1 MΩ Offset Error2 25°C ±1.5 mV Offset Drift ±7 µV/°C Gain Error Internal full-scale calibration3, 25°C ±0.05 % of FS Gain Drift ±1 ppm/°C Integral Nonlinearity (INL) ±0.01 % of FSR Total Unadjusted Error (TUE)4 Internal full-scale calibration 25°C, internal VREF ±0.06 % of FSR −40°C to +105°C, internal VREF ±0.1 % of FSR 25°C, external VREF ±0.06 % of FSR −40°C to +105°C, external VREF ±0.08 % of FSR Power Supply Rejection AVDD for VIN = 1 V 70 dB Common-Mode Rejection VIN = 1 V At DC 85 dB At 50 Hz, 60 Hz 20 Hz output data rate (postfilter), 50 Hz ± 1 Hz and 60 Hz ± 1 Hz 120 dB Normal Mode Rejection4 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB Resolution See Table 6 and Table 8 Noise See Table 6 and Table 8 CURRENT INPUTS Input Current Range −0.5 +24 mA Absolute (Pin) Input Voltage AVSS −0.05 AVDD +0.055 V Input Impedance6 54 60 75 Ω Offset Error2 ±2 µA Offset Drift ±3 nA/°C Gain Error Factory calibrated gain, 25°C ±0.02 % of FS Gain Drift ±10 ppm/°C INL ±0.01 % of FSR TUE4 25°C, internal VREF ±0.08 % of FSR −40°C to +105°C, internal VREF ±0.2 % of FSR 25°C, external VREF ±0.08 % of FSR −40°C to +105°C, external VREF ±0.2 % of FSR Power Supply Rejection AVDD for IIN = 10 mA 0.5 µA/V Normal Mode Rejection4 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB Resolution See Table 7 and Table 9 Noise See Table 7 and Table 9 ADC SPEED AND PERFORMANCE ADC Output Data Rate (ODR) One channel, see Table 6 1.25 31,250 SPS No Missing Codes4 Excluding sinc3 filter ≥ 15 kHz notch 24 Bits |
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