AD4112BCPZ datasheet(27/58 Pages) AD

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Data Sheet

AD4112

Rev. A | Page 27 of 58

CURRENT INPUTS

There are four current input pins (IIN0+ to IIN3+) and four

current return pins (IIN0− to IIN3−). Connect these pins in

numbered pairs (for example, IIN0+ and IIN0−).

Disable the input buffers for the current inputs.

To achieve specified accuracy, the current channels are factory

calibrated. This calibration value is stored in on-chip nonvolatile

memory and is copied to all gain registers after a power-up or reset.

VOLTAGE INPUTS

The AD4112 can be set up to have eight single-ended inputs or

four fully differential inputs. The voltage divider on the analog

front end has a division ratio of 10 and consists of precision

matched resistors that enable an input range of ±20 V from a

single 5 V power supply.

Enable the input buffers in the setup register for voltage input

channels.

Fully Differential Inputs

Due to the matching resistors on the analog front end, the

differential inputs must be paired together in the following

pairs: VIN0 and VIN1, VIN2 and VIN3, VIN4 and VIN5, and

VIN6 and VIN7. If any two voltage inputs are paired in a

configuration other than what is described in this data sheet,

the accuracy of the device cannot be guaranteed.

Single-Ended Inputs

The user can also choose to measure up to eight different

single-ended voltage inputs. In this case, each of the voltage

inputs must be paired with VINCOM. Connect VINCOM

externally to AVSS.

Adjusting Voltage Input Gain

After a power up or reset, all gain registers are loaded with factory

calibration coefficients for current inputs. When using a voltage

input, the corresponding gain register must be modified after

powering up or resetting the device. Perform this modification

by running an internal full-scale calibration (see the Calibration

section for more information). Alternatively, the gain register

can be overwritten with a nominal value of 0x55567C. However,

a calibration is recommended because the ideal value varies

from device to device.

Alternatively, the gain can be calibrated by connecting a

precision voltage source to the voltage input and performing a

full-scale system calibration.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 00 … 00, a midscale voltage

resulting in a code of 100 … 000, and a full-scale input voltage

resulting in a code of 111 … 111. The output code for any input

voltage is represented as

Code = (2N × VIN × 0.1)/VREF

The output code for any input current is represented as

Code = (2N × IIN × 50 Ω)/VREF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000 … 000, a zero differential input voltage resulting in

a code of 100 … 000, and a positive full-scale input voltage

resulting in a code of 111 … 111. The output code for any

analog input voltage can be represented as

Code = 2N –1 × ((VIN × 0.1/VREF) + 1)

The output code for any input current is represented as

Code = 2N− 1 × ((IIN × 50 Ω/VREF) + 1)

where:

N = 24.

VIN is the input voltage.

VREF is the reference voltage.

IIN is the input current.

AD4112 REFERENCE

The AD4112 offers the user the option of either supplying an

external reference to the REF+ and REF− pins of the device,

using AVDD – AVSS, or by allowing the use of the internal

2.5 V, low noise, low drift reference. Select the reference source

to be used by the analog input by setting the REF_SELx bits,

Bits[5:4], in the setup configuration registers appropriately. The

structure of the Setup Configuration 0 register is shown in Table 19.

By default, the AD4112 uses an external reference on power-up.

Internal Reference

The AD4112 includes a low noise, low drift voltage reference.

The internal reference has a 2.5 V output. The internal reference

is output on the REFOUT pin after the REF_EN bit in the ADC

mode register is set and is decoupled to AVSS with a 0.1 μF

capacitor. The AD4112 internal reference is disabled by default

on power-up.

AD4112BCPZ Datasheet(PDF) 27 Page - Analog Devices

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