HMC8415LP6GETR datasheet(20/23 Pages) AD

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HMC8415LP6GE

Data Sheet

Rev. A | Page 20 of 23

RECOMMENDED BIAS SEQUENCE

Power-Up Bias Concept for the EV1HMC8415LP6G with

the Pulsor

A proper set of dc bias conditions always requires that the gate

be biased to a voltage that does not result in excessive drain

current, regardless of whether the drain bias is constant or

pulsed. For this reason, always apply a gate bias voltage to

Pulsor J1-VG1 prior to the application of a voltage to Pulsor J1-

VDD. VG1 = −6 V is considered a safe starting value. With a

pulsed logic signal applied to Pulsor J1-PULSE and 28 V applied

to Pulsor J1-VDD, a pulsed voltage between 0 V (for PULSE =

logic low) and VDD = 28 V (for PULSE = logic high) becomes

available at Pulsor J2-VDD_PULSE and Pulsor J3-VDD_PULSE

and, therefore, at the drains of the device under test (DUT).

When the gate bias voltage (applied to Pulsor J1-VG1) is

available at the gates simultaneously with VDD_PULSE at the

drains, a drain current proportional to VG1 flows. VG1 can be

adjusted until the target pulsed IDQ is achieved. With this pulsor

board, J1-VDD has a 35 V maximum above which damage can

occur to the pulsor.

The J1-PULSE and VDD_PULSE pulse width and duty cycle

limits for reliable operation are as follows:



Pulse width = 500 μs maximum



Duty cycle = 20% maximum

Power-Down Bias Concept for the EV1HMC8415LP6G

with the Pulsor

The power-down bias sequence follows from the power-up bias

sequence. Bring Pulsor J1-PULSE to logic low to remove

VDD_PULSE, and then power down Pulsor J1-VDD followed

by powering down Pulsor J1-VG1.

HMC8415LP6GETR Datasheet(PDF) 20 Page - Analog Devices