LM75

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4

DETAILED OPERATING DESCRIPTION

A typical LM75 hardware connection is shown in Figure 1.

Figure 1. Typical Application

+V DD

A 0

A 1

A 2

SDA

SCL

TCN75

C Bypass

7

6

5

1

3

2

8

Address

(Set as Desired)

Interface

4

0.1

mF Recommended

Unless Device is

Mounted Close to CPU

Two Wire

INT/CMPTR

Serial Data (SDA)

Bidirectional. Serial data is transferred in both directions

using this pin.

Serial Clock (SCL)

Input. Clocks data into and out of the LM75.

INT/CMPTR

Open Collector, Programmable Polarity. In Comparator

Mode, unconditionally driven active any time temperature

INT/CMPTR will become inactive when temperature

and

Programmer’s

Model.)

In

Interrupt

Mode,

unconditionally reset to its inactive state by reading any

register via the 2–wire bus. If and when temperature falls

the INT/CMPTR output is unconditionally reset upon

entering Shutdown Mode. If programmed as an active–low

output, it can be wire–ORed with any number of other open

collector devices. Most systems will require a pull–up

resistor for this configuration.

Note that current sourced from the pull–up resistor causes

power dissipation and may cause internal heating of the

LM75. To avoid affecting the accuracy of ambient

temperature readings, the pull–up resistor should be made as

large as possible. INT/CMPTR’s output polarity may be

programmed by writing to the INT/CMPTR POLARITY bit

in the CONFIG register. The default is active low.

Address (A2, A1, A0)

Inputs. Sets the three least significant bits of the LM75

8–bit address. A match between the LM75’s address and the

address specified in the serial bit stream must be made to

initiate

communication

with

the

LM75.

Many

protocol–compatible devices with other addresses may

share the same 2–wire bus.

Slave Address

The four most significant bits of the Address Byte (A6,

A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and

A0 in the serial bit stream must match the states of the A2,

A1 and A0 address inputs for the LM75 to respond with an

Acknowledge (indicating the LM75 is on the bus and ready

to accept data). The Slave Address is represented by:

LM75 Slave Address

1

0

0

1

A2

A1

A0

MSB

LSB

Comparator/Interrupt Modes

INT/CMPTR behaves differently depending on whether

the LM75 is in Comparator Mode or Interrupt Mode.

Comparator Mode is designed for simple thermostatic

operation. INT/CMPTR will go active anytime TEMP

it will reset to its inactive state. The state of INT/CMPTR is

maintained in shutdown mode when the LM75 is in

comparator mode. In Interrupt Mode, INT/CMPTR will

until any register is read via the 2–wire bus. Interrupt Mode

is better suited to interrupt driven microprocessor–based

systems. The INT/CMPTR output may be wire–OR’ed with

other interrupt sources in such systems. Note that a pull–up

resistor is necessary on this pin since it is an open–drain

output. Entering Shutdown Mode will unconditionally reset

INT/CMPTR when in Interrupt Mode.

SHUTDOWN MODE

When the appropriate bit is set in the configuration

register (CONFIG) the LM75 enters its low–power

shutdown

mode

temperature–to–digital conversion process is halted. The

or SCL due to external bus activity may increase the standby

power consumption. If the LM75 is in Interrupt Mode, the

state of INT/CMPTR will be RESET upon entering

shutdown mode.

Fault Queue

To lessen the probability of spurious activation of

INT/CMPTR the LM75 may be programmed to filter out

transient events. This is done by programming the desired

value into the Fault Queue. Logic inside the LM75 will

prevent the device from triggering INT/CMPTR unless the

programmed number of sequential temperature–to–digital

conversions yield the same qualitative result. In other words,