Electronic Components Datasheet Search
  English  ▼

X  

HD64F2145 Datasheet(PDF) 428 Page - Renesas Technology Corp

Part # HD64F2145
Description  Hitachi 16-Bit Single-Chip Microcomputer
PDF  829 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2145 Datasheet(HTML) 428 Page - Renesas Technology Corp

Back Button HD64F2145 Datasheet HTML 424Page - Renesas Technology Corp HD64F2145 Datasheet HTML 425Page - Renesas Technology Corp HD64F2145 Datasheet HTML 426Page - Renesas Technology Corp HD64F2145 Datasheet HTML 427Page - Renesas Technology Corp HD64F2145 Datasheet HTML 428Page - Renesas Technology Corp HD64F2145 Datasheet HTML 429Page - Renesas Technology Corp HD64F2145 Datasheet HTML 430Page - Renesas Technology Corp HD64F2145 Datasheet HTML 431Page - Renesas Technology Corp HD64F2145 Datasheet HTML 432Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 428 / 829 page
background image
Rev. 2.0, 08/02, page 388 of 788
Reception: Before making a transition to module stop, software standby, watch, sub-active, or
sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If a transition is made
during data reception, the data being received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 15.27 shows a sample flowchart for mode transition during reception.
Start transmission
Transmission
[1]
No
No
No
Yes
Yes
Yes
Read TEND flag in SSR
Make transition to software standby mode etc.
Cancel software standby mode etc.
TE = 0
Initialization
TE = 1
[2]
[3]
All data transmitted?
Change operating mode?
TEND = 1
[1] Data being transmitted is lost
halfway. Data can be normally
transmitted from the CPU by
setting TE to 1, reading SSR,
writing to TDR, and clearing
TDRE to 0 after mode
cancellation; however, if the DTC
has been initiated, the data
remaining in DTC RAM will be
transmitted when TE and TIE are
set to 0.
[2] Also clear TIE and TEIE to 0
when they are 1.
[3] Module stop, watch, sub-active,
and sub-sleep modes are
included.
Figure 15.24 Sample Flowchart for Mode Transition during Transmission



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com