OV9650 datasheet(13/26 Pages) OMNIVISION

13 / 26 page

Version 1.7, December 3, 2004

Proprietary to OmniVision Technologies

Omni ision

COM2

Common Control 2

Bit[7:5]: Reserved

Bit[4]:

Soft sleep mode

Bit[3:2]: Reserved

Bit[1:0]: Output drive capability

00: 1x

01: 2x

10: 2x

11: 4x

PID

Product ID Number MSB (Read only)

VER

Product ID Number LSB (Read only)

COM3

Common Control 3

Bit[7]:

Reserved

Bit[6]:

Output data MSB and LSB swap

Bit[5:4]: Reserved

Bit[3]:

Pin selection

Change RESET pin to EXPST_B (frame exposure

mode timing) and change PWDN pin to FREX (frame

exposure enable)

Bit[2]:

VarioPixel for VGA, CIF, QVGA, QCIF, QQVGA, and

QQCIF

Bit[1]:

Reserved

Bit[0]:

Single frame output (used for Frame Exposure mode only)

COM4

Common Control 4

Bit[7]:

VarioPixel for QVGA, QCIF, QQVGA, and QQCIF

Bit[6:3]: Reserved

Bit[2]:

Tri-state option for output clock at power-down period

Tri-state at this period

No tri-state at this period

Bit[1]:

Tri-state option for output data at power-down period

Tri-state at this period

No tri-state at this period

Bit[0]:

Reserved

COM5

Common Control 5

Bit[7]:

System clock selection. If the system clock is 48 MHz, this

bit should be set to high to get 15 fps for YUV or RGB

Bit[6:5]: Reserved

Bit[4]:

Slam mode enable

Master mode

Slam mode (used for slave mode)

Bit[3:0]: Reserved

Table 5

Device Control Register List (Continued)

Address

(Hex)

Name

Default

(Hex)

R/W

Description

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