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LMS7002M Datasheet(PDF) 13 Page - List of Unclassifed Manufacturers

Part # LMS7002M
Description  FPRF MIMO Transceiver IC With Integrated Microcontroller
PDF  27 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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LMS7002M Datasheet(HTML) 13 Page - List of Unclassifed Manufacturers

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LMS7002M
13
LMS7002M
– FPRF MIMO Transceiver IC
ENABLE_IQ_SEL_n
FCLK_n
DIQ[11:0]_n
...
...
...
...
...
I(k-3)A
Q(k-3)A
I(k-3)B
Q(k-3)B
I(k-2)A
I(k-1)A
I(k)A
Q(k-2)A
Q(k-1)A
Q(k)A
I(k-2)B
I(k-1)B
Q(k-2)B
Q(k-1)B
tSetup
tSetup
tHold
tHold
...
Note: n = 1 for LimeLight Port 1, n = 2 for LimeLight Port 2.
Figure 38: Transmit data path (TRXIQ double data rate (DDR) mode)
ENABLE_IQ_SEL_n
MCLK_n
DIQ[11:0]_n
...
...
...
...
...
I(k-3)A
Q(k-3)A
I(k-2)A
I(k-1)A
I(k)A
Q(k-2)A
Q(k-1)A
tSetup
tHold
...
Note: n = 1 for LimeLight Port 1, n = 2 for LimeLight Port 2.
Figure 39: Receive data path (TRXIQ single data rate (SDR) mode)
ENABLE_IQ_SEL_n
FCLK_n
DIQ[11:0]_n
...
...
...
...
...
I(k-3)A
Q(k-3)A
I(k-2)A
I(k-1)A
I(k)A
Q(k-2)A
Q(k-1)A
tSetup
tHold
...
Note: n = 1 for LimeLight Port 1, n = 2 for LimeLight Port 2.
Figure 40: Transmit data path (TRXIQ single data rate (SDR) mode)
Implementing Low Voltage Digital IQ Interface
Digital IO buffers of LMS7002M are supplied using four pins (pin name
– DIGPRVDD2, pin ID – W33, T32, H32, AH30). All these pins must be
supplied by the same supply DVDD. There is one additional supply pin
(pin name
– DIGPRPOC, pin ID – W31) which performs Power On
Control (POC) function for digital pads. To implement a low voltage
digital interface, DVDD can be lowered to 1.8V. If DVDD=1.8V then all
data lines in Figure 41 must also be set to 1.8V CMOS IOs for correct
interface operation.
1.8V
– 3.3V
DVDD
DIGPRVDD2 (W33)
DIGPRVDD2 (T32)
DIGPRVDD2 (H32)
DIGPRVDD2 (AH30)
DIGPRPOC (W31)
IO Buffers
Supplies
LMS7002M
/
12
DIQ[11:0]_1
ENABLE_IQSEL_1
TXNRX_1
FCLK_1
MCLK_1
/
12
DIQ[11:0]_2
ENABLE_IQSEL_2
TXNRX_2
FCLK_2
MCLK_2
1
st Channel
Interface
2
nd Channel
Interface
Figure 41: Digital IQ interface supplies
IQ Interface Timing Parameters
Parameter
Min.
Typ.
Max.
Unit
Data Setup Time (tSETUP)
1
ns
Data Hold Time (tHOLD )
0.2
ns
Data Output Delay (tOD) at 15 pF load
6
ns
Table 6: Digital IQ interface timing parameters with 2.5V IO supply
Digital IQ Interface IO Buffers Specifications
Parameter
Min.
Typ.
Max.
Unit
Condition
Supply Voltage (PVDD)
1.7
2.5
3.6
V
Can go below 2.5V nominal to support LV CMOS signalling
Input High VIH
PVDD-0.8
V
Input Low VIL
0.8
V
Output High VOH
PVDD-0.4
V
Output Low VOL
0.4
V
Input Pad Capacitance CIN
3.5
pF
Output Drive Current
8
12
mA
Programmable
Table 7: Digital IO buffers specifications at 2.5V supply



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