LMS7002M datasheet(2/27 Pages) ETC2

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LMS7002M

– FPRF MIMO Transceiver IC

GENERAL DESCRIPTION

LMS7002M is a fully integrated, multi-band, multi-standard RF

transceiver that is highly programmable. It combines Low Noise

Amplifiers

(RXLNA),

Power

Amplifier

Drivers

(TXPAD)

receiver/transmitter (RX/TX) mixers, RX/TX filters, synthesizers, RX

gain control, TX power control, the analog-to-digital and digital-to-

analog convertors (ADC/DACs) and has been designed to require very

few external components.

The top level architecture of LMS7002M transceiver is shown in Figure

1. The chip contains two transmit and two receive chains for achieving a

Multiple In Multiple Out (MIMO) platform. Both transmitters share one

PLL and both receivers share another. Transmit and receive chains are

all implemented as zero Intermediate Frequency (zero IF or ZIF)

architectures providing up to 160MHz RF modulation bandwidths

(equivalent to 80MHz baseband IQ bandwidth). For the purpose of

simplifying this document, the explanation for the functionality and

performance of the chip is based on one transmit and one receive

circuitry, given that the other two work in exact the same manner.

On the transmit side, In-phase and Quadrature IQ DAC data samples,

from the base band processor, are provided to the LMS7002M via the

LimeLight

™ digital IQ interface. LimeLight™ implements the JESD207

standard IQ interface protocol as well as de facto IQ multiplexed

standard. JESD207 is Double Data Rate (DDR) by definition. In IQ

multiplexed mode LimeLight

™ also supports Single Data Rate (SDR).

The IQ samples are then pre-processed by the digital Transceiver

Signal Processor (TSP) for minimum analog / RF distortion and applied

to the on chip transmit DACs. The DACs generate analog IQ signals

which are provided for further processing to the analog/RF section.

Transmit low pass filters (TXLPF) remove the images generated by

zero hold effect of the DACs, as well as the DAC out-of-band noise. The

analog IQ signals are then mixed with the transmit PLL (TXPLL) output

to produce a modulated RF signal. This RF signal is then amplified by

one of two separate / selectable power amplifier drivers and two open-

drain differential outputs are provided as RF output for each MIMO

path.

The LMS7002M provides an RF loop back option which enables the TX

RF signal to be fed back into the baseband for calibration and test

purposes. The RF loop back signal is amplified by the loopback

amplifier in order to increase the dynamic range of the loop.

There are two additional loop back options implemented, one is an

analog base band (BB) loop back and another is a digital loop back

(DLB) as shown in Figure 1. The analog loop back is intended for

testing while the DLB can be used to verify the LMS7002M connectivity

to base band, FPGA, DSP or any other digital circuitry.

On the receive side, three separate inputs are provided each with a

dedicated LNA optimised for narrow or wide band operation. Each port

RF signal is first amplified by a programmable low noise amplifier

(RXLNA). The RF signal is then mixed with the receive PLL (RXPLL)

output to directly down convert to baseband. AGC steps can be

implemented by a BB trans-impedance amplifier (RXTIA) prior to the

programmable bandwidth low pass channel select / anti alias filters

(RXLPF). The received IQ signal is further amplified by a programmable

gain amplifier RXPGA. DC offset is applied at the input of RXTIA to

prevent saturation and to preserve the receive ADC’s dynamic range.

The resulting analog receive IQ signals are converted into the digital

domain with on-chip receive ADCs. Following the ADCs, the signal

conditioning is performed by the digital Transceiver Signal Processor

(TSP) and the resulting signals are then provided to the BB via the

LimeLight

™ digital IQ interface.

The analog receive signals can also be provided off chip at RXOUTI

and RXOUTQ pins by closing the RXOUT switch. In this case it is

possible to power down the on chip ADCs/TSP and use external parts

which can be very useful for more resource demanding applications or

where higher signal resolution is required. A similar option is also

available on the TX side where the analog signal can be processed by

external components. The on chip DACs/TSP can be powered down

and analog inputs can be provided at TXINI and TXINQ pins.

There is on chip integrated temperature sensor which base band

modem can read via the SPI and trigger re-calibration of the chip if

significant chip/ambient temperature change is observed.

Parameter

Min.

Typ.

Max.

Unit

Condition/Comment

Operating Temperature Range

-40

°C

Storage Temperature Range

-65

125

°C

Operating Frequency Range

0.1

3800

MHz

Extended by TSP NCOs

RF Modulation Bandwidth

160

MHz

Through digital interface (MIMO)

Through digital interface (SISO)

Through analog interface

Frequency Resolution

24.8

Using 52 MHz PLL reference clock

Analog Supply Voltage, High (VDDAH)

1.71

1.8

1.89

Used for TXPAD

Analog Supply Voltage, Medium

(VDDAM)

1.33

1.4

1.47

Generated using integrated low-dropout regulators

(LDOs)

Analog Supply Voltage, Low (VDDAL)

1.2

1.25

1.3

Generated using integrated LDOs

Digital Core Supply Voltage

1.1

1.2

1.3

Generated using integrated LDOs

Digital Peripheral (IO) Supply Voltage

1.7

2.5

3.6

TX Supply Current

350

At -7 dBm output power, 2x2 MIMO, including the DACs

and TSP

RX Supply Current

420

For 2x2 MIMO, including the ADCs and TSP

Maximum RF Output Power

dBm

Continuous Wave

PLL Reference Clock

MHz

Reference and Other Spurs Level

-100

dBm

Measured at TX RF output or RX RF input

IQ Imbalance Image

-70

dBc

After calibration

Interpolation/Decimation digital filters

stop band suppression

108

Table 1: General specifications

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