LMS7002M datasheet(17/27 Pages) ETC2

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LMS7002M

– FPRF MIMO Transceiver IC

TXFCLK

RXMCLK

DACs

ADCs

RX TSP

TX TSP

DAC

Clock

ADC

Clock

RXD[11:0]

TXD[11:0]

DACs/ADCs Block

CLKMUX

FFDIV

Clock PLL

Fractional-N

REFCLK

CLKGEN Block

Figure 47: Clock generation and distribution

CALIBRATION AND INITIALIZATION

There are a number of calibrations which the LMS7002M can carry out

internally when instructed via the SPI. These calibrations can be

initiated on power up/reset to produce optimum settings. Initialization

and calibration steps are summarized below.

Initialization

•

Power up the chip. In case of using multiple off chip LDOs,

power up sequence is not important.

•

Apply RESET pulse (active low). This sets all the

configuration registers to their default values.

•

Overwrite some registers defaults if required.

Available calibration options and recommended order of execution

•

On-chip resistor and capacitor calibration

•

TX, RX and clock synthesizer VCO tuning

•

TX and RX analog LPF pass band tuning

•

RX DC offset and RX LO leakage cancellation

•

TX DC offset and TX LO leakage cancellation

•

TX IQ imbalance calibration

•

RX IQ imbalance calibration

This section shows three key calibration algorithms. Others are either

similar or very simple.

Please see the “LMS7002M Programming and

Calibration Guide” and other relevant application notes for more details.

VCO Tuning

In order to lock RF or clock synthesiser while having phase noise close

to optimum, VCO capacitance has to be selected carefully. A flexible

algorithm, based on monitoring on chip Vtune comparators state, is

described below.

Assuming the synthesiser is configured for target LO/clock frequency

(correct VCO powered up, integer and fractional part of the divider set,

…), Figure 48 shows typical measured Vtune variation with the

VCOCAP codes for the two target LO frequencies, 1.95GHz and

2.14GHz. Obviously, Vtune is changing from 1.17V down to 0.05V.

However, PLL lock is guaranteed only when Vtune is in the range

between Vth Low and Vth High. Vth High is fixed to 0.92V while Vth

Low can be programmed to be 0.18V or 0.1V. For the best phase noise

performance, Vtune should be kept around the middle of the Vth Low

and Vth High range.

There are two on chip Vtune comparators per synthesiser: CMPH and

CMPL. Their threshold voltages are set to Vth High=0.92V and Vth

Low=0.18V or 0.1V. The state of the comparators can be obtained by

powering them up and reading the corresponding SPI register. True

table is given below.

CMPH

CMPL

Status

OK, Vtune in range

Vtune is high (> 0.92V), PLL lock not guaranteed.

Vtune is low (< 0.18V or <0.1V), PLL lock not guaranteed.

Not possible.

These can be used to choose VCOCAP code. All we need to find is the

code CMIN when comp

arators change the state from “00” to “10” and

the code CMAX when the comparators change the state from “10” to

“11”. Optimum VCOCAP code is then the middle one between CMIN

and CMAX. For LO=2.4GHz, this is illustrated in Figure 48. Once the

synthesiser is set, Vtune comparators can also be used as lock (in

range) indication.

Figure 48: VCO capacitance selection

Analog Filters Pass Band Tuning

As shown in Figure 6 and Figure 7, LMS7002M has six analog low pass

filtering stages. Pass band of each stage can independently be

programmed and/or tuned. Tuning is very useful as it takes into account

process, temperature, sample-to-sample and voltage supply variations.

The algorithm uses on chip options as follows:

•

TXNCO generates digital test tones (CW).

•

Digital test tones are converted into analog by the DACs.

•

INVERSE sinc filter must be enabled to flatten DACs

amplitude response.

•

LMS7002M is set into either base-band or RF TX-to-RX loop

back mode.

•

Only LPF being tuned should be enabled. Other TX and RX

filters should be bypassed or widely open.

•

Loop back signal is converted back into digital domain by the

ADCs.

•

Digital RX RSSI block measures the amplitude of the loop

back signal.

In this set up TXNCO test tone drives the filter input while filter output is

measured by RSSI block which enables filter amplitude response to be

determined.

All filtering stages are implemented as active RC blocks hence their

pass band is controllable by changing resistors and/or capacitors. Only

two parameters per stage are available to change via SPI: one for filter

resistors control and another one for capacitors control. If resistors

control parameter is changed then all resistors within the filter are

scaled equally. If capacitors control code is changed then all capacitors

within the filter are scaled equally. Therefore, component ratio is kept

constant

which

preserves

designed

filter

amplitude

response

(Chebyshev for example) disregarding the control codes.

There are two types of filter stages: trans-impedance (TXLPFLAD,

TXLPFH, RXTIA) and voltage gain (TXLPFS5, RXLPFL, RXLPFH).

Tuning is essentially the same for all stages with minor differences

between trans-impedance and voltage gain types. The algorithm is two

steps process described below and illustrated in Figure 49.

Step 1: Check point

TXNCO generates very low frequency (close to DC) test tone (200kHz

in Figure 49 example) which is by design guaranteed to be within filter

pass band for all possible RC values.

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