GC5018 datasheet(89/115 Pages) TI

89 / 115 page

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4.4.5

DDC Channel Controls

GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

ragc2_accum(15:0) : lower 16 bits of the ragc2 error accumulator.

4.4.4.62

RAGC2_ACCUM_MSB Register

Address: 0x3D

READ ONLY

BIT 15

BIT 8

ragc2_accum(31:24)

BIT 7

BIT 0

ragc2_accum (23:16)

ragc2_accum(31:16) : upper 16 bits of the ragc2 error accumulator.

4.4.4.63

RAGC3_ACCUM_LSB Register

Address: 0x3E

READ ONLY

BIT 15

BIT 8

ragc3_accum(15:8)

BIT 7

BIT 0

ragc3_accum (7:0)

ragc3_accum(15:0) : lower 16 bits of the ragc3 error accumulator.

4.4.4.64

RAGC3_ACCUM_MSB Register

Address: 0x3F

READ ONLY

BIT 15

BIT 8

ragc3_accum(31:24)

BIT 7

BIT 0

ragc3_accum (23:16)

ragc3_accum(31:16) : upper 16 bits of the ragc3 error accumulator.

4.4.5.1

FIR_MODE Register

Address: 0x0

BIT 15

BIT 8

cdma_mode

unused

crastarttap_pfir(4:0)

GC5018 GENERAL CONTROL

GC5018 Datasheet(PDF) 89 Page - Texas Instruments

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