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GC5018 Datasheet(PDF) 21 Page - Texas Instruments

Part # GC5018
Description  8-CHANNEL WIDEBAND RECEIVER
PDF  115 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

GC5018 Datasheet(HTML) 21 Page - Texas Instruments

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3.2.5
DDC Channel Delay Adjust and Zero Insertion
18
input rate
samples from
Mixer
read offset
3
insert offset
sync (zero stuff moment)
Zero
Pad
18
I
Q
Delay Memory
I:8 slots x 18−bits
Q:8 slots x 18−bits
18
18
18
18
I
Q
3
full rxclk rate
samples to
CIC Filter
sync (offset registers)
interpolation
(number of zeros stuffed between samples)
3
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
Table 3-1. Examples of Decimation and Sample Rates
(1)
Input
Zeros
rxclk(MHz) and
CIC
CIC Out-
CFIR
CFIR
PFIR
PFIR Out-
Output
Sample
Added
Zero Pad
Decimation
put Rate
Decimation
Output
Decimation
put Rate
Decimation
Rate
Output Rate
(MSPS)
Rate
(MSPS)
(MSPS)
(MSPS)
(MSPS)
UMTS
122.88
0
122.88
8
15.36
2
7.68
1
7.68
1
UMTS
92.16
0
92.16
6
15.36
2
7.68
1
7.68
1
UMTS
76.80
1
153.6
10
15.36
2
7.68
1
7.68
1
UMTS
61.44
1
122.88
8
15.36
2
7.68
1
7.68
1
CDMA
122.88
0
122.88
25
4.9152
2
2.4576
1
2.4576
1
CDMA
78.6432
0
78.6432
16
4.9152
2
2.4576
1
2.4576
1
CDMA
78.6432
1
157.2864
32
4.9152
2
2.4576
1
2.4576
1
CDMA
61.44
1
122.88
25
4.9152
2
2.4576
1
2.4576
1
TD-SCDMA
92.16
0
92.16
18
5.12
2
2.56
1
2.56
2
TD-SCDMA
81.92
0
81.92
16
5.12
2
2.56
1
2.56
2
TD-SCDMA
76.80
0
76.80
15
5.12
2
2.56
1
2.56
2
TD-SCDMA
76.80
1
153.6
30
5.12
2
2.56
1
2.56
2
TD-SCDMA
1
122.88
24
5.12
2
2.56
1
2.56
2
(1)
The DDC output interfaces, both serial and parallel formats, can be programmed to decimate by 2. For the TD-SCDMA examples listed
above, the DDC output rate is 1.28Msps (1x chip rate).
The Receive Channel Delay Adjust function is used to add programmable delays in the channel
downconvert path. Adjusting channel delay can be used to compensate for analog elements external to
the GC5018 digital downconversion such as cables, splitters, analog downconverters, filters, etc.
The Delay Memory block consists of an 8 register memory and a state machine. The state machine uses
a counter to control the write (input) pointer, and the programmed read offset register data to create a
read (output) pointer. Programming larger read offset register values increases the effective delay at a
resolution equal to the input sample rate.
The Zero Pad block is used in conjunction with the Delay Memory for delay adjustments. For example,
with input rates of rxclk/8, the Zero Pad block interpolates the input data to rxclk by inserting 7 zeros. The
Zero Pad’s sync insert offset 3-bit control specifies when the zeros are inserted relative to the Sync signal.
This permits a fine adjustment at the rxclk resolution.
RECEIVE DIGITAL SIGNAL PROCESSING
21



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