GC5018 datasheet(13/115 Pages) TI

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data to FIFO for rxin_a

data to FIFO for rxin_b

data to FIFO for rxin_c

data to FIFO for rxin_d

rxin_a

Test and

Noise

Generator

sync

rxin_b

rxin_c

rxin_d

slf_tst_ena

rduz_sens_ena

Test and

Noise

Generator

Test and

Noise

Generator

Test and

Noise

Generator

lfsr(17)

lfsr(16)

rxin _X(15:0)

lfsr (15:0)

to FIFO for rxin _X

nz_pwr_mask(15:0)

16 XORs

16 ANDs

rduz_sens_ena

GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

The LFSR circuits can also be used to add noise to the rxin_a/b/c/d input signals by setting the

rduz_sens_ena control register bit. The magnitude of the noise added can be adjusted by programming

the nz_pwr_mask(15:0) control register. In the figure below, X = {a,b,c or d}.

PROGRAMMING

VARIABLE

DESCRIPTION

slf_tst_ena

When set, the test signal generators replace the rxin_a/b/c/d input signals with internally generated

psuedo random sequences. The fifo_bypass bit must be set when this bit is set.

rduz_sens_ena

Enables the LFSR, adding noise to the ADC input data when set.

nz_pwr_mask(15:0)

Selects the power of the noise added to the ADC input data.

adc_fifo_bypass

When set, the FIFO is essentially bypassed, and the adcclk_a/b/c/d clock input ports are ignored.

ddc_counter(31:0)

32 bit general purpose counter interval

ddc_counter_width(7:0)

8 bit general purpose counter timeout width pulse

ssel_ddc_counter(2:0)

Sync source selection for the general purpose counter

self_test_constant(17:0)

18-bit self test constant value applied to all 4 rxin_a/b/c/d inputs when self_test_const_ena is set.

self_test_const_ena

Enables the self test constant value for rxin_a/b/c/d

RECEIVE DIGITAL SIGNAL PROCESSING

GC5018 Datasheet(PDF) 13 Page - Texas Instruments

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