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DLPC900 Datasheet(PDF) 8 Page - Texas Instruments |
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DLPC900 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 83 page  8 DLPC900 DLPS037D – OCTOBER 2014 – REVISED MARCH 2019 www.ti.com Product Folder Links: DLPC900 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated (1) Several options allow reconfiguration of the DMD interface in order to better optimize board layout. The DLPC900 can swap channel A with channel B. The DLPC900 can also swap the data bit order within each channel independent of swapping the A and B channels. (2) The DLPC900 is a full-bus DMD signaling interface. Figure 18 shows the controller connections for this configuration. (3) Refer to I/O Type and Subscript Definition (Table 1). DMD LVDS Interface Pin Functions PIN(1)(2) I/O POWER I/O TYPE (3) CLK SYSTEM DESCRIPTION NAME NUMBER DCKA_P DCKA_N V4 V3 VDD18 O7 DCKA_P DCKA_N DMD, LVDS interface channel A, differential clock. SCA_P SCA_N V2 V1 VDD18 O7 DCKA_P DCKA_N DMD, LVDS interface channel A, differential serial control. DDA_P_15 DDA_N_15 DDA_P_14 DDA_N_14 DDA_P_13 DDA_N_13 DDA_P_12 DDA_N_12 DDA_P_11 DDA_N_11 DDA_P_10 DDA_N_10 DDA_P_9 DDA_N_9 DDA_P_8 DDA_N_8 P4 P3 P2 P1 R4 R3 R2 R1 T4 T3 T2 T1 U4 U3 U2 U1 VDD18 O7 DCKA_P DCKA_N DMD, LVDS interface channel A, differential serial data. DDA_P_7 DDA_N_7 DDA_P_6 DDA_N_6 DDA_P_5 DDA_N_5 DDA_P_4 DDA_N_4 DDA_P_3 DDA_N_3 DDA_P_2 DDA_N_2 DDA_P_1 DDA_N_1 DDA_P_0 DDA_N_0 W4 W3 W2 W1 Y2 Y1 Y4 Y3 AA2 AA1 AA4 AA3 AB2 AB1 AC2 AC1 DCKB_P DCKB_N J3 J4 VDD18 O7 DCKB_P DCKB_N DMD, LVDS interface channel B, differential clock. SCB_P SCB_N J1 J2 VDD18 O7 DCKB_P DCKB_N DMD, LVDS interface channel B, differential serial control. |
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