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SAF-C161PI Datasheet(PDF) 105 Page - Infineon Technologies AG |
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SAF-C161PI Datasheet(HTML) 105 Page - Infineon Technologies AG |
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105 / 400 page  &3, ,QWHUUXSW DQG 7UDS )XQFWLRQV User’s Manual 5-23 1999-08 5.7 Interrupt Node Sharing Interrupt nodes may be shared between several module requests either if the requests are generated mutually exclusive or if the requests are generated at a low rate. If more than one source is enabled in this case the interrupt handler will first have to determine the requesting source. However, this overhead is not critical for low rate requests. This node sharing is controlled via the sub-node interrupt control register ISNC which provides a separate request flag and enable bit for each supported request source. The interrupt level used for arbitration is determined by the node control register (...IC). Note: In order to ensure compatibility with other derivatives application software should never set reserved bits within register ISNC. ISNC Intr. Subnode Ctrl. Reg. ESFR (F1DE H/EFH) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - --- -- -- --- - PLL IE PLL IR RTC IE RTC IR - - - - - - - - - - - - rw rw rw rw Bit Function xxIR Interrupt Request Flag for Source xx 0: No request from source xx pending. 1: Source xx has raised an interrupt request. xxIE Interrupt Enable Control Bit for Source xx 0: Source xx interrupt request is disabled. 1: Source xx interrupt request is enabled. Table 5-7 Sub-node Control Bit Allocation Bit pos. Interrupt Source Associated Node 15...4 Reserved. Reserved. 3|2 PLL / OWD XP3IC 1|0 RTC XP3IC |
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