© VITESSE SEMICONDUCTOR CORPORATION

Page 7

8/31/98

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7128

Hex Port Bypass Circuit / Dual Repeater

for 1.0625 Gb/s FC-AL Disk Arrays

G52177-0, Rev. 2.3

Table 2: Pin Description

Pin #

Name

Description

16, 15

63, 62

IN1+, IN1-

IN2+, IN2-

INPUT - Differential. Serial input to CRU1/CRU2 (AC Coupling recommended)

20, 19

60, 59

OUT1+, OUT1-

OUT2+, OUT2-

OUTPUT - Differential. Serial output from MUX7/PBC6 (AC Coupling recommended).

26, 25

29, 28

38, 37

41, 40

51, 50

54, 53

LSI1+, LSI1-

LSI2+, LSI2-

LSI3+, LSI3-

LSI4+, LSI4-

LSI5+, LSI5-

LSI6+, LSI6-

INPUT - Differential. Serial input from disk drive ‘x’ to PBCx (AC Coupling

23, 22

32, 31

35, 34

44, 43

47, 46

57, 56

LSO1+, LSO1-

LSO2+, LSO2-

LSO3+, LSO3-

LSO4+, LSO4-

LSO5+, LSO5-

LSO6+, LSO6-

OUTPUT - Differential. Serial output from PBCx to disk drive ‘x’ (AC Coupling

recommended).

24, 30

36, 42

49, 55

1, 13

SEL1, SEL2

SEL3, SEL4

SEL5, SEL6

SEL7, SEL8

INPUT - TTL.

A LOW bypasses the disk drive input and passes the output from the

previous PBC to the output of PBCx. A HIGH selects the disk drive input (LSIx) as the

output of the PBC. SEL7 configures MUX7. SEL8 configures MUX8.

2

REFCLK

INPUT - TTL.. REFerence CLocK at 1/10th or 1/20th the baud rate (Nominally 53.125 or

106.25 MHz) as determined by RFSEL. Used for internal clock multiplier unit.

3

RFSEL

INPUT - TTL. ReFclk SELect. When HIGH, REFCLK is 1/10th the baud rate and would

normally be 106.25 MHz. When LOW, REFCLK is 1/20th the baud rate (53.125 MHz)

4, 14

FAIL1-

FAIL2-

OUTPUT - TTL. When LOW, indicates that the output of CRU1/2 does not contain valid

Fibre Channel data.

12

FAILSEL

INPUT - TTL. Selects the algorithm to drive the FAIL1-/FAIL2- outputs. When HIGH,

the “Multiple Frame Error Mode” is used. When LOW, the “Single Frame Error Mode” is

selected.

7,

10,

11

TEST1

TEST2

TEST3

INPUT - TTL. LOW for factory test, HIGH for normal operation.

5, 17, 27,

48, 64

VDD

Power Supply. 3.3V Supply.

21, 33, 45, 58

VDD1, VDD2,

VDD3, VDD4

High-Speed Output Power Supply. 3.3V Supply for PECL drivers. VDD1 powers OUT1

and LSO1, VDD2 powers LSO2 and LSO3, VDD3 powers LSO4 and LSO5, VDD4

powers LSO6 and OUT2. If the pair of outputs are not used, VDDx may be grounded to

conserve power.

8

VDDA

Analog Power Supply. 3.3V for Clock Multiplier PLL.

6, 9, 18, 39,

52, 61

VSS

Ground.