VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7128

Hex Port Bypass Circuit / Dual Repeater

for 1.0625 Gb/s FC-AL Disk Arrays

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

8/31/98

G52177-0, Rev. 2.3

Functional Description

A Port Bypass Circuit contains a differential 2:1 mux operating at 1.0625 Gb/s. The input to the PBC is

always passed to the LSOx output of the PBC to let the disk drive monitor loop activity. The mux selects either

the disk drive’s input, LSIx, or the input from the previous PBC as determined by the SELx input which is nor-

mally connected directly to the disk drives EN_BYP output. When SELx is HIGH, the mux selects the disk

drive input, LSIx. When SELx is LOW, the mux bypasses the disk drive input and passes the output of the pre-

vious PBC to the output of the PBC. Two extra muxes help route serial signals. MUX7 passes either the output

of PBC6 (bypass mode) or the output of CRU2 (normal mode) to MUX8/OUT1 depending whether SEL7 is

LOW or HIGH. MUX8 passes either the output of CRU1 or the output of MUX7 to PBC1 depending on

whether SEL8 is HIGH or LOW.

A TTL reference clock, REFCLK, is used by the internal Clock Multiplier Unit (CMU) to generate a baud

rate clock at 1.0625 Gb/s.

If RFSEL is HIGH, the CMU multiplies REFCLK (nominally 106.25MHz) by a

factor of 10. If RFSEL is LOW, the CMU multiplies REFCLK (nominally 53.125MHz) by a factor of 20. The

user must ensure that RFSEL is properly set in order to match the frequency of REFCLK.

Two fully integrated Clock Recovery Units (CRUs) are provided to improve signal quality and determine

whether the input to the repeater is a valid Fibre Channel signal. Each repeater consists of a Clock Recovery

Unit (CRU) and a digital Signal Detect Unit (SDU). The CRU locks onto the incoming signal, generates a

recovered clock (at 1.0625 GHz) and uses this clock to resynchronize the incoming signal. The recovered data

has improved signal quality due to amplification and jitter attenuation. Recovered data is retimed to the recov-

ered clock, not to REFCLK. The design of the CRU eliminates the need for any Lock-to-Reference signal since,

in the absence of data, the CRU locks onto REFCLK automatically thereby eliminating the need for any exter-

nal control circuitry.

The Signal Detect Units (SDUs) tests the output of the CRUs for valid Fibre Channel data by detecting run

length errors (more than 5 consecutive 1's or 0's) and the absence of a seven bit pattern found in the K28.5 char-

acter of either disparity (‘0000101’ or ‘1111010’). This K28.5 pattern should occur multiple times between

frames. The maximum length of a Fibre Channel frame is 2148 bytes (or 21,480 encoded bits) and the SDU

divides time into ~31 microsecond time intervals (2^15 bit times). At the end of each interval, any run length or

K28.5 errors which occurred during the interval are stored internally for use by the state machine which drives

the SDU output, FAILx-.

The FAILSEL input controls both SDUs and the FAILx- outputs provide the status of each SDU. FAILSEL

selects two different modes generated by the SDU; Single Frame (LOW) or Multiple Frame (HIGH) Error

Mode. In Single Frame Error Mode, any error condition that occurs within an interval causes FAILx- to be

asserted LOW immediately after that interval. FAILx- remains asserted until immediately after an error-free

interval occurs. In Multiple Frame Error Mode, FAILx- is asserted after four consecutive intervals containing

errors and remains asserted until four consecutive error-free intervals occur.

The intent of the Multiple Frame

Error Mode is to allow FAIL1- or FAIL2- to be directly connected to the mux controls, SEL8 or SEL7, in order

to configure the part to isolate IN1 or IN2 whenever valid data is not present. Single Frame Error Mode allows

the user to develop their own algorithm for monitoring data and controlling MUX8 or MUX7.