DLPC4422AZPC datasheet(29/49 Pages) TI1

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DLPC4422

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DLPS074 – FEBRUARY 2017

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Feature Description (continued)

7.3.5 Video Graphics Processing Delay

The DLPC4422 controller introduces a variable number of field/ frame delays dependent on the source type and

selected processing steps performed on the source. For optimum audio/ video synchronization this delay must

be matched in the audio path. The following tables define various video delay scenarios to aid in audio matching.

Frame and Fields in table refer to source frames and fields.

•

For 2-D sources, “N” is defined to be the ratio of the primary channel source frame rate (or field rate for

interlaced video) to the display frame/ field rate.

•

For 3-D sources, “M” is defined to be the ratio of the primary channel source frame rate (or field rate for

interlaced video) required to obtain both the left and right image, to the display frame/field rate (The rate at

which each eye is displayed).

Table 3. Primary Channel/Video-Graphics Processing Delay

Source

3D Video

Decoder

De-Interlacing

Frame Rate

Conversion

FRC Type

Formatter Buffer

Total Delay

50 to 60 Hz

Interlaced SDTV

Video

Disabled

2 Fields

Sync (1:4)

M Fields

2 + M Fields

60Hz Progressive

Video

Disabled

2 Frames

Sync (1:4)

M Frames

2 + M Frames

120Hz

Progressive Video

Disabled

2 Frames

Sync (1:2)

M Frames

2 + M Frames

24Hz 1080p

Disabled

1 Frame

Sync (1:6)

M Frames

1 + M Frames

50 to 60 Hz

(720p, 1080p)

Disabled

1 Frame

Sync (1:2)

M Frames

1 + M Frames

50 to 60 Hz

1080p

Disabled

1 Frame

Sync (1:2)

M Frames

1 + M Frames

60Hz Interlaced

Graphics (VGA-

WUXGA)

Disabled

1 Field

Sync (1:4)

M Frames

1 + M Frames

60 Hz Graphics

Disabled

1 Frame

Sync (1:4)

M Frames

1 + M Frames

120 Hz Graphics

Disabled

1 Frame

Sync (1:2)

M Fields

1 + M Fields

50 to 60 Hz

Interlaced

Disabled

1 Field

Sync(1:2)

M Fields

1 + M Fields

50 to 60 Hz

Progressive

Disabled

1 Frame

Sync(1:2)

M Frames

1 + M Frames

(1)

Assumes a maximum single direction trace length of 75 mm.

7.3.6 Program Memory Flash/SRAM Interface

The DLPC4422 controller provides three external program memory chip selects:

•

PM_CSZ_0 – available for optional SRAM or flash device (

≤ 128 Mb)

•

PM_CSZ_1 – dedicated CS for boot flash device (ie. Standard NOR-type flash,

≤ 128 Mb)

•

PM_CSZ_2 – available for optional SRAM or flash device (

≤ 128 Mb)

Flash and SRAM access timing is software programmable up to 31 wait states. Wait state resolution is 6.7 ns in

normal mode and 53.33 ns in low power modes. Wait state program values for typical flash access times are

shown in the Table 4.

Table 4. Wait State Program Values for Typical Flash Access Times

Normal Mode (1)

Low Power Mode(1)

Formula to Calculate the

Required Wait State Value

= Roundup (Device_Access_Time / 6.7 ns)

= Roundup

(Device_Access_Time / 53.33

ns)

Max Supported Device Access

Time

207 ns

1660 ns

DLPC4422AZPC Datasheet(PDF) 29 Page - Texas Instruments

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