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DLPC4422AZPC Datasheet(PDF) 7 Page - Texas Instruments

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Part # DLPC4422AZPC
Description  DLPC4422 DLP Display Controller
PDF  49 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DLPC4422AZPC Datasheet(HTML) 7 Page - Texas Instruments

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DLPC4422
www.ti.com
DLPS074 – FEBRUARY 2017
Product Folder Links: DLPC4422
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Pin Configurations and Functions (continued)
PIN
(1)
I/O
(2)
DESCRIPTION
NAME
NO.
ALF_HSYNC
AD11
I4
Autolock dedicated horizontal sync. This signal includes an internal pull-down and
uses hysteresis.
ALF_CSYNC
AE11
I4
Autolock dedicated composite sync (sync on green). This signal includes an internal
pull-down and uses hysteresis.
DMD RESET and BIAS CONTROL
DADOEZ
AE7
O5
DAD1000 / DAD2000 Output Enable (active low)
DADADDR_3
AD6
O5
DAD1000 / DAD2000 address
DADADDR_2
AE5
O5
DADADDR_1
AF4
O5
DADADDR_0
AB8
O5
DADMODE_1
AD7
O5
DAD1000 / DAD2000 modes
DADMODE_0
AE6
O5
DADSEL_1
AE4
O5
DAD1000 / DAD2000 select
DADSEL_0
AC7
O5
DADSTRB
AF5
O5
DAD1000 / DAD2000 strobe
DAD_INTZ
AC8
I4
DAD1000 / DAD2000 interrupt (active low). This signal typically requires an external
pull-up and uses hysteresis.
DMD LVDS INTERFACE
DCKA_P
V4
O7
DMD, LVDS I/F channel A, differential clock
DCKA_N
V3
O7
SCA_P
V2
O7
DMD, LVDS I/F channel A, differential serial control
SCA_N
V1
O7
DDA_P_15
P4
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_15
P3
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_14
P2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_14
P1
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_13
R4
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_13
R3
O7
DMD, LVDS I/F channel A, differential serial data
Input Bus B Data bit 9.
100-Ω internal LVDS termination.
DDA_P_12
R2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_12
R1
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_11
T4
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_11
T3
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_10
T2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_10
T1
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_9
U4
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_9
U3
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_8
U2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_8
U1
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_7
W4
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_7
W3
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_6
W2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_6
W1
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_5
Y2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_5
Y1
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_4
Y4
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_4
Y3
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_3
AA2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_3
AA1
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_2
AA4
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_2
AA3
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_1
AB2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_1
AB1
O7
DMD, LVDS I/F channel A, differential serial data
DDA_P_0
AC2
O7
DMD, LVDS I/F channel A, differential serial data
DDA_N_0
AC1
O7
DMD, LVDS I/F channel A, differential serial data
DCKB_P
J3
O7
DMD, LVDS I/F channel A, differential clock
DCKB_N
J4
O7
DMD, LVDS I/F channel A, differential clock



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