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Model 626

Very Low Jitter LVPECL or LVDS Clock

DOC# 008-0586-0 Rev. C

Page 3 of 10

Electrical Specifications

Enable Truth Table

Pin 1

Pin 4 & Pin 5

Logic ‘1’

Output

Open

Output

Logic ‘0’

High Imp.

Test Circuit

LVPECL

LVDS

Output Waveform

LVPECL or LVDS

Output Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Start Up Time

-

3

10

ms

Enable Function [Standby]

Enable Input Voltage

Pin 1 Logic '1', Output Enabled

-

-

V

Disable Input Voltage

Pin 1 Logic '0', Output Disabled

-

-

V

Disable Time

Pin 1 Logic '0', Output Disabled

-

-

200

ns

Standby Current

Pin 1 Logic '0', Output Disabled

-

-

15

µA

Enable Time

Pin 1 Logic '1', Output Enabled

-

-

4

ms

40MHz - 220MHz, Bandwidth 12kHz to 20MHz

-

300

500

fs

6MHz - 39.999MHz, Bandwidth 12kHz to 5MHz

-

-

<1

ps

Phase Jitter, RMS

tjrms