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Model 626

Very Low Jitter LVPECL or LVDS Clock

DOC# 008-0586-0 Rev. C

Page 8 of 10

Mechanical Specifications

Package Drawing

Marking Information

Recommended Pad Layout

Pin Assignments

Notes

Pin

Symbol

Function

1

EOH

Enable

2

N.C.

No Connect

3

GND

Circuit & Package Ground

4

Output

RF Output

5

Output

Complimentary RF Output

6

Supply Voltage

Table I - Date Code

2001

2005

2009

2013

2017

A

B

C

D

E

F

G

H

J

K

L

M

2002

2006

2010

2014

2018

N

P

Q

R

S

T

U

V

W

X

Y

Z

2003

2007

2011

2015

2019

a

b

c

d

e

f

g

h

j

k

l

m

2004

2008

2012

2016

2020

n

p

q

r

s

t

u

v

w

x

y

z

NOV

DEC

YEAR

MAY

JUN

JUL

AUG

SEP

OCT

MONTH

JAN

FEB

MAR

APR

Preferred

1. O – Output Type; P = LVPECL, L = LVDS.

2. ST – Frequency Stability/Temperature Code.

[Refer to Ordering Information]

3. V – Voltage Code; 3 = 3.3V, 2 = 2.5V.

4. xxxx – Frequency Code.

3-digits, frequencies below 100MHz

4-digits, frequencies 100MHz or greater

[See document 016-1454-0, Frequency Code Tables.]

5. D – Date Code. See Table I for codes.

[Note: Manufacturing site code must appear on reel

and carton labels.]

Optional

1. O – Output Type; P = LVPECL, L = LVDS.

2. ST – Frequency Stability/Temperature Code.

[Refer to Ordering Information]

3. xxxx – Frequency Code.

3-digits, frequencies below 100MHz

4-digits, frequencies 100MHz or greater

[See document 016-1454-0, Frequency Code Tables.]

4. D – Date Code. See Table I for codes.

[Note: Manufacturing site code must appear on reel

and carton labels.]

626OSTV

● xxxxD

1. JEDEC termination code (e4). Barrier-plating is

nickel [Ni] with gold [Au] flash plate.

2. Reflow conditions per JEDEC J-STD-020; +260°C

maximum, 20 seconds.

3. MSL = 1.

626OST

● xxxxD