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CS4384 Datasheet(PDF) 36 Page - Cirrus Logic |
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CS4384 Datasheet(HTML) 36 Page - Cirrus Logic |
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36 / 50 page ![]() 36 DS620A1 CS4384 Function: These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether PCM or DSD mode is selected. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 9-21. 5.3.2 Functional Mode (FM) Default = 11 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates) Function: Selects the required range of input sample rates or Auto Speed Mode. 5.4 DSD Control (address 04h) 5.4.1 DSD Mode Digital Interface Format (DSD_DIF) Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate) Function: The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital Interface Format pins. DIF3 DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE 00 0 0 Left Justified, up to 24-bit data 0 9 00 0 1 I2S, up to 24-bit data 1 10 00 1 0 Right Justified, 16-bit data 2 11 00 1 1 Right Justified, 24-bit data 3 12 01 0 0 Right Justified, 20-bit data 4 13 01 0 1 Right Justified, 18-bit data 5 14 10 0 0 One-line Mode 1, 24-bit Data +SDIN4 8 15 10 0 1 One-line Mode 2, 20-bit Data +SDIN4 9 17 10 1 0 One-line Mode 3, 24-bit 6-channel 10 18 10 1 1 One-line Mode 4, 20-bit 6-channel 11 20 11 0 0 TDM 12 21 XX X X All other combinations are Reserved Table 7. Digital Interface Formats - PCM Mode 765 4 3 2 1 0 DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD STATIC_DSD INVALID_DSD DSD_PM_MD DSD_PM_EN 000 0 1 1 0 0 |
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