CS5368 datasheet(15/39 Pages) CIRRUS

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DS624A1

CS5368

SERIAL AUDIO INTERFACE - I²S/LJ TIMING

The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 30 pF, timing threshold is 50% of VLS.

Notes:

In Master mode, the SCLK/LRCK ratio is fixed at 64. In Slave Mode, the SCLK/RCLK ratio can be set ac-

cording to preference. However, chip performance is guaranteed only when using the ratios in Section

4.6.9

Master and Slave Clock Frequencies on page 29.

Figure 2. I²S/LJ Timing

Parameter

Symbol

Min

Typ

Max

Unit

Sample Rates

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

108

216

kHz

SCLK Frequency1

SCLK Period

1/(64*216 kHz)

SCLK Duty Cycle

tPERIOD

tHIGH

72.3

64*Fs

LRCK setup

before SCLK rising

LRCK hold

after SCLK rising

tSETUP1

tHOLD1

SDOUT setup

before SCLK rising

SDOUT hold

after SCLK rising

tSETUP2

tHOLD2

LRCK

SDOUT

SCLK

data

channel

data

HOLD2

SET UP2

HOLD1

SET UP1

PERIOD

HIGH

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