CS5368 datasheet(23/39 Pages) CIRRUS

23 / 39 page

DS624A1

CS5368

Figure 9. Master Slave Clock Flow

4.6.3

Synchronization of Multiple Devices

To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK

must be the same for all of the CS5368s in the system. If only one Master clock source is needed, one

solution is to place one CS5368 in Master mode, and slave all of the other devices to the one master. If

multiple Master clock sources are needed, a possible solution would be to supply all clocks from the same

external source and time the CS5368 reset de-assertion with the falling edge of MCLK. This will ensure

that all converters begin sampling on the same clock edge.

Figure 10. Master and Slave Clocking for a 32-Channel Application

4.6.4

Sample Rate Ranges

Supported sampling rates are 2 kHz-216 kHz divided into three ranges: 2 kHz-54 kHz, 54 kHz-108 kHz,

and 108 kHz-216 kHz. These sampling speed modes are called Single-Speed Mode, Double-Speed

Mode and Quad-Speed Mode (SSM, DSM, QSM), respectively.

4.6.5

Using M1 and M0 to Set Sampling Parameters

The Master/Slave operation and the sample rate range are controlled through the settings of the M1 and

M0 pins in Stand-Alone Mode, or by the M[1] and M[0] bits in the Global Mode Control Register in Control-

Port Mode.

Table 2. M1 and M0 Settings

Mode

Frequency Range

Single-Speed Master Mode

2 kHz - 54 kHz

Double-Speed Master Mode

54 kHz - 108 kHz

Quadruple-Speed Master Mode

108 kHz - 216 kHz

Auto-Detected Speed Slave Mode

2 kHz - 216 kHz

ADC as

timing

master

Controller

LRCK

SCLK

ADC as

timing

slave

Controller

LRCK

SCLK

Master

CS5368

Slave1

CS5368

Slave2

CS5368

Slave3

CS5368

SCLK & LRCK/FS

CS5368 Datasheet(PDF) 23 Page - Cirrus Logic

CS5368 Datasheet(HTML) 23 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Datasheet Download

Link URL