CS5368 datasheet(18/39 Pages) CIRRUS

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DS624A1

CS5368

SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING

(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL =30pF)

Notes:

Data must be held for sufficient time to bridge the transition time of CCLK.

For fsck <1 MHz

For fsck <1 MHz.

Figure 5. SPI Timing

Parameter

Symbol

Min

Max

Units

CCLK Clock Frequency

fsck

06.0

MHz

RST Rising Edge to CS Falling

tsrs

CS Falling to CCLK Edge

tcss

CS High Time Between Transmissions

tcsh

1.0

µs

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time1

tdh

CCLK Falling to CDOUT Stable

tpd

-50

Rise Time of CDOUT

tr1

-25

Fall Time of CDOUT

tf1

-25

Rise Time of CCLK and CDIN2

tr2

100

Fall Time of CCLK and CDIN3

tf2

-100

CCLK

CDIN

CDOUT

RST

srs

scl

sch

css

csh

dsu

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