LT4256-3

11

42563f

APPLICATIO S I FOR ATIO

To reduce inrush current, increase C1 or decrease load

capacitance. If the voltage across the current sense resis-

ited by the internal current limit circuitry. The voltage on

GATE is adjusted to maintain a constant voltage across the

sense resistor and TIMER begins to charge.

threshold, PWRGD goes high.

Undervoltage and Overvoltage Detection

to determine when it is safe to turn on the load and allow

the user the greatest flexibility for setting the operational

thresholds. UV and OV are internally connected to an

analog window comparator. Any time that UV goes below

3.6V or OV goes above 4V, GATE will be pulled low until the

UV/OV voltages return to the normal operation voltage

window (4V and 3.6V, respectively).

The UV threshold should never be set below the internal

UVLO threshold (9.8V typically) because the benefit of the

UV’s hysteresis will be lost, making the LT4256-3 more

is at its 3.6V threshold). UV is filtered with C3 to prevent

noise spikes and capacitively coupled glitches from shut-

ting down the LT4256-3 output erroneously.

To calculate UV and OV thresholds, use the following

equations:

4256 F07

R5

0.010

Ω

LT4256-3

SENSE

13

10

5

7

8

16

D2

SMAT70A

15

1

2

4

9

GATE

FB

12

PWRGD

RETRY

UV

OV

TIMER

GND

48V

(SHORT PIN)

Q1

IRF540

D1

CMPZ5241BS

11V

R3

4.02k

R2

4.02k

Q2

VN2222

R1

64.9k

R7

100

Ω

R9

4.02k

R6

10

Ω

R8

36.5k

48V

4A

R4

51k

C2

33nF

C3

0.01

µF

OFF SIGNAL

FROM MPU

C1

10nF

OPEN

UV = 36V

OV = 73V

PWRGD = 40V

GND

+

Figure 7. How to Use a Logic Signal to Control the LT4256-3 Turn On/Off

RR

R

V

V

a

R

RR

V

b

kR

R

R

k

VV

R

RR

VV

RR

R

THUVLH

THOVLH

THUVHL

THOVHL

12

3

4

12

3

12

4

1

2

20

1

2

3

200

3

36

1

1

23

4

36

1

12

3

=+







()

=

+

()

Ω≤

+

+

≤

Ω

()

=+

+









()

=+

+









–

–

.;

.

Figure 7 shows how the LT4256-3 is commanded to shut

off with a logic signal. This is accomplished by pulling the

gate of the open-drain MOSFET, Q2, (tied to UV) high.