LT4256-3IGN datasheet(16/20 Pages) LINER

16 / 20 page

LT4256-3

42563f

In some applications it may be possible for VOUT to ring

below ground (due to the parasitic trace inductance).

Higher current applications, especially where the output

load is physically far away from the LT4256-3 will be more

susceptible to these transients. This is normal and the

LT4256-3 has been designed to allow for some ringing

below ground. However, if the application is such that

VOUT can ring more than 3V below ground, damage may

occur to the LT4256-3 and an external diode, D2, from

ground (anode) to VOUT (cathode) will have to be added to

the circuit as shown in Figure 15 (it is critical that the

reverse breakdown voltage of the diode be higher than the

highest expected VCC voltage). A capacitor placed from

ground to VOUT directly at the LT4256-3 pins can help

reduce the amount of ringing on VOUT but it may not be

enough for some applications.

During a fault condition, the LT4256-3 pulls down on

GATE with a switch capable of sinking about 62mA. Once

GATE drops below the output voltage by a diode forward

voltage, the external Zener will forward bias and VOUT will

also be discharged to GND. In addition to the GATE

capacitance, the output capacitance will be discharged

through the LT4256-3.

In applications utilizing very large external N-channel

MOSFETs, the possibility exists for the MOSFET to turn on

when initially inserted into a live backplane (before the

APPLICATIO S I FOR ATIO

LT4256-3 becomes active and pulls down on GATE). This

is due to the MOSFET intrinsic drain to gate capacitance

forcing current into R7 and C1 when the drain voltage

steps up from ground to VCC with an extremely fast rise

time. To alleviate this situation, a diode, D3, should be put

across R7 with the cathode connected to C1 as shown in

Figure 16.

Whenever the LT4256-3 turns the MOSFET off, GATE pulls

the MOSFET gate to ground with an open collector capable

of sinking 62mA. If the output is held up by a large

reservoir capacitor, the stored energy is dissipated in the

pull-down transistor via a sneak path through the (now

forward biased) Zener, D1. The LT4256-3 has a propri-

etary feature that reduces on-chip power dissipation by

sensing when the MOSFET is off and reducing the pull-

down current significantly. See VGATE Turn-Off for more

information about using this feature.

VGATE Turn-Off

The LT4256-3 has a proprietary feature that reduces

power dissipation by sensing when the MOSFET is off and

reducing the pull-down current significantly. As the GATE

pin is discharged during any fault, the LT4256-3 monitors

the GATE pin and VOUT pin. When the GATE pin is 2V below

VOUT, the pull-down current is reduced from 62mA to

about 130

µA.

Figure 15. Negative Output Voltage Protection Diode Application

4256 F14

0.010

Ω

LT4256-3

SENSE

VCC

GATE

VOUT

PWRGD

RETRY

TIMER

GND

VCC

48V

(SHORT PIN)

IRF540

CMPZ5241BS

11V

MRA4003T3

4.02k

64.9k

100

Ω

4.02k

Ω

36.5k

VOUT

48V

51k

33nF

0.01

µF

10nF

OPEN

UV = 36V

OV = 73V

PWRGD = 40V

GND

SMAT70A

LT4256-3IGN Datasheet(PDF) 16 Page - Linear Technology

LT4256-3IGN Datasheet(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL